Abstract: A matched filter having a set of registers to successively store a digital voltage. The matched filter includes a cumulative shift register, a number of exclusive-or circuits, and an analog adder. The cumulative shift register has a number of stages in which each stage has one bit corresponding to the shift register. The exclusive-or circuits each perform an exclusive-or function on each bit of the digital data and the one bit coefficient while the analog adder sums outputs from the exclusive-or circuits.

Abstract: An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

Abstract: A plurality of sets of spreading code sequences are stored in registers and selectively supplied to matched filters. The soft-handover, multi-code processing and long-delay paths can be processed by a small circuit.

Abstract: A matched filter bank including a plurality of matched filters and a sampling and holding units commonly used by the total matched filters. Therefore, the circuit size is diminished. An inverting amplifier for the matched filter with a variable gain includes an input capacitance, an inverting amplifier connected to an output of the input capacitance, and a plurality of feedback capacitances connected between an input and output of the inverting amplifier. A plurality of switches are connected to input side of the feedback capacitances for alternatively connecting the feedback capcitanec to the input of the inverting amplifier or a reference voltage. The feedback capacitances connected to the reference voltage are invalid with respect to a composite capacitance of the feedback capacitance and have no influence to the amplifier.

Abstract: A 3-step cell search type receiver apparatus with an improved accuracy is provided. The receiver apparatus comprises a matched filter MF and sliding correlator unit SC to which a reception signal Sin is inputted. The matched filter MF computes correlation between the reception signal Sin and a primary synchronization code PSC and produces an output Spsc, which is retained in a memory MEM1 and then processed by a timing detection unit TDP. The sliding correlator unit SC comprises a plurality of sliding correlators SC1 to SCq, whose outputs A [1] to A [q] are retained in a memory MEM2 and then processed by a timing group identification unit TGI. The sliding correlator unit SC computes correlation based on the primary and secondary synchronization codes or the secondary synchronization code. In the former case, inphase-addition is performed after performing channel estimation and phase correction, and in the latter case, only inphase-correction is performed.

Abstract: A radio telecommunication apparatus 1 is provided with a pager receiver 2, cellular radio device 3, and a control portion 4 for controlling the entire apparatus and supplying power to the cellular radio device 3 according to a message received through the radio calling system. When located within an area of a radio calling system, the portable terminal 1 performs location registration to the radio calling system through the cellular system, disconnects power to the cellular radio device 3, and enters the radio calling standby state. When there is an incoming call to the cellular radio device 3, that portable terminal is called through the radio calling system and the power is turned on to the cellular radio device 3.

Abstract: An object of the present invention is to provide an interleaver and a deinterleaver, which are small-sized and power saving. An address converter ACON has three counters CNT1, CNT2 and CNT3 in associated with a first rank through a third rank and the outputs DO11, DO12 and DO13 of respective counters CNT1, CNT2 and CNT3 are inputted in lookup tables LUT1, LUT2 and LUT3. In the counter CNT3, a clock CK1 with a predetermined cycle is inputted and the numeric values of “O” through “3” are repeatedly outputted. In the counter CNT2, a carry out CO3 to be outputted in synchronization with the output of the counter CNT3, i.e., “O” is inputted as a clock CK2. Further, the counter CNT2 outputs the numeric values of “O” through “4” repeatedly. In the counter CNT1, a carry out CO2 to be outputted in synchronization with the output of the counter CNT2, i.e., “O” is inputted as a clock CK3.

Abstract: A signal reception apparatus for DS-CDMA communication system having a complex matched filter for despreading a received signal into I- and Q-components Di and Dq of despread signal. Dj and Dq are input to a path selection portion 13 for extracting a phase error in a pilot symbol block of the despread signal. A phase compensation signal is calculated according to the phase error in the portion 13. An information symbol is compensated according to the phase compensation signal. An electrical power is calculated from an average of the phase compensation signal of several slots for selecting paths to be received. The selected paths are combined with phase synchronized by a rake combiner 14.

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

Abstract: A matched filter and signal reception apparatus having a low power consumption and small circuitry size. In the matched filter, an analog input signal is converted to digital data by an analog to digital (A/D) converter, digital multiplication, as a correlation calculation, is executed by a plurality of exclusive-OR circuits, and an addition of outputs of the exclusive-OR circuits is performed. In the digital multiplication, the digital data is multiplied by a spreading code of one bit. The outputs from the exclusive-OR circuits are added for each weight of bits, and the addition output results are weighted and summed together.

Abstract: A receiver for spread spectrum communication system receives a traffic channel and common control channel by a plurality of matched filters at least one of which is selectively available for the traffic or the common control channel. At the initial acquisition, a plurality of matched filters are used for receiving the common control channel. At the hand-over, a plurality of matched filters are used to receive traffic channels of the current base station and the base stations in the adjacent cells.

Abstract: An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

Abstract: A filter circuit comprises a plurality of sampling and holding circuits for sampling and holding analog input signal with a predetermined sampling period, a calculation circuit for multiplying each the analog input signal by a predetermined multiplier, and for summing the multiplication results. The sampling and holding circuits are controlled in an electrical power such that the electrical power is decreased when holding.

Abstract: A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks.

Abstract: An output of analog complex matched filter is simplified to be a one dimensional signal such as electrical power. Multi-path detection is performed by the simplified signal. The output of the matched filter is received and processed only when peaks occur in the one dimensional signal.

Abstract: The present invention provides a path-diversity system featuring a small-size phase compensating circuit. This circuit calculates a compensating coefficient according to the signals of a pilot block or a pair of pilot blocks surrounding an information block, and then compensates information signals thereafter by the calculated compensating coefficient.

Abstract: The present invention has an object to provide a spread spectrum communication system for heightening the speed of communication. The present invention transfers the first PN code sequence itself as the first component, adds and transfers zero or more instances of the second PN code sequence given a phase difference as the second component, and defines an information for transmitting by the number of the second PN codes corresponding to a cycle of said first PN code sequence.

Abstract: In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit.

Abstract: A complex multiplication circuit of a calculation formula equivalent but different from the usual formula.The calculation formula is as follows:Pr={x(a+b)-b(x+y)} equivalent to (ax-by)Pi={y(a-b)+b(x+y)} equivalent to (ay+bx)Here,Input signal: x+jyMultiplier:a+jbMultiplication result:Pr+jPi.

Abstract: In a method is disclosed for transmitting and receiving a transmission data signal, after the transmission data signal is generated, it is modulated by a first time spread root Nyquist filter to generate a transmission signal. The signal is then transmitted and received, whereupon the signal is transformed into a baseband signal. The baseband signal is then demodulated through a second time spread root Nyquist filter to revive the transmission data signal. An apparatus is also disclosed that performs this method. In addition, methods of separately transmitting and receiving signals are also described.