Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: A processing device and a method of processing data between a plurality of modules in the processing device. The method includes monitoring packets exchanged between a transmission module and a reception module from among the plurality of modules; determining whether a task being executed by the processing device has switched based on the monitored packets; when the task being executed by the processing device has switched, obtaining a packet layout encoded by taking into account transitions to occur due to processing of data packets regarding the switched task; and executing the switched task by using data packets to which the obtained packet layout is applied.

Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: A processing device and a method of processing data between a plurality of modules in the processing device. The method includes monitoring packets exchanged between a transmission module and a reception module from among the plurality of modules; determining whether a task being executed by the processing device has switched based on the monitored packets; when the task being executed by the processing device has switched, obtaining a packet layout encoded by taking into account transitions to occur due to processing of data packets regarding the switched task; and executing the switched task by using data packets to which the obtained packet layout is applied.

Abstract: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

Abstract: A reconfigurable processor, a code conversion apparatus thereof, and a code conversion method are provided. The reconfigurable processor includes a processor including functional units (FUs) and execution modes, the execution modes including a Very Long Instruction Word (VLIW) mode based on a first FU group, a first Coarse-Grained Array (CGA) mode based on FUs of a second FU group, and a second CGA mode based on predetermined ones of the FUs of the second FU group.

Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.