Patents by Inventor Changsheng Chen

Changsheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070288308
    Abstract: A method and system of establishing affinity of two job listings is disclosed. A first job listing is identified. The first job listing has a first job listing attribute. A second job listing is identified. The second job listing has a second job listing attribute. A first job listing attribute value and a second job listing attribute value are compared to determine if the first job listing attribute and the second job listing attribute are similar according to a predefined set of rules. The first job listing and the second job listing are affiliated if the first job listing attribute and the second job listing attribute are determined to be similar.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 13, 2007
    Applicant: Yahoo Inc.
    Inventors: Changsheng Chen, Adam Hyder
  • Publication number: 20070273909
    Abstract: A method and system of establishing affinity of job listings is disclosed. A first job listing for which a jobseeker has applied is determined. The first job listing has a first job attribute. A second job listing for which the jobseeker has applied is also determined. The second job listing has a second job attribute. A first job attribute value and a second job attribute value are compared to determine a similarity score that represents a similarity between the first job attribute and the second job attribute. The first job listing and the second job listing are affiliated if the similarity score is higher than a predefined threshold level.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 29, 2007
    Applicant: YAHOO! Inc.
    Inventors: Changsheng Chen, Adam Hyder
  • Publication number: 20060265268
    Abstract: A job searching and matching system and method is disclosed that gathers job seeker information in the form of job seeker parameters from one or more job seekers, gathers job information in the form of job parameters from prospective employers and/or recruiters, correlates the information with past job seeker behavior, parameters and behavior from other job seekers, and job parameters and, in response to a job seeker's query, provides matching job results based on common parameters between the job seeker and jobs along with suggested alternative jobs based on the co-relationships and based on ratings and preferences provided by the job seeker and provides negative filtration of undesirable jobs based on job seeker input and in response to queries from the system in order to efficiently and accurately accommodate job seeker perception.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 23, 2006
    Inventors: Adam Hyder, Changsheng Chen
  • Publication number: 20060265269
    Abstract: A job searching and matching system and method is disclosed that gathers job seeker information in the form of job seeker parameters from one or more job seekers, gathers job information in the form of job parameters from prospective employers and/or recruiters, correlates the information with past job seeker behavior, parameters and behavior from other job seekers, and job parameters and, in response to a job seeker's query, provides matching job results based on common parameters between the job seeker and jobs along with suggested alternative jobs based on the co-relationships and based on ratings and preferences provided by the job seeker and provides negative filtration of undesirable jobs based on job seeker input and in response to queries from the system in order to efficiently and accurately accommodate job seeker perception.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 23, 2006
    Inventors: Adam Hyder, Changsheng Chen
  • Publication number: 20060265270
    Abstract: A job searching and matching system and method is disclosed that gathers job seeker information in the form of job seeker parameters from one or more job seekers, gathers job information in the form of job parameters from prospective employers and/or recruiters, correlates the information with past job seeker behavior, parameters and behavior from other job seekers, and job parameters and, in response to a job seeker's query, provides matching job results based on common parameters between the job seeker and jobs along with suggested alternative jobs based on the co-relationships and based on ratings and preferences provided by the job seeker in response to queries from the system in order to efficiently and accurately accommodate job seeker perception.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 23, 2006
    Inventors: Adam Hyder, Changsheng Chen
  • Publication number: 20060265267
    Abstract: A job searching and matching system and method is disclosed that gathers job seeker information in the form of job seeker parameters from one or more job seekers, gathers job information in the form of job parameters from prospective employers and/or recruiters, correlates the information with past job seeker behavior, parameters and behavior from other job seekers, and job parameters and, in response to a job seeker's query, provides matching job results based on common parameters between the job seeker and jobs along with suggested alternative jobs based on the co-relationships.
    Type: Application
    Filed: May 23, 2005
    Publication date: November 23, 2006
    Inventors: Changsheng Chen, Adam Hyder, Sandeep Khanna
  • Patent number: 6954130
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: October 11, 2005
    Assignee: ChipScale, Inc.
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Patent number: 6946734
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 20, 2005
    Assignee: ChipScale, Inc.
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Patent number: 6833986
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: December 21, 2004
    Assignee: ChipScale, Inc.
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Publication number: 20040160727
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 19, 2004
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Publication number: 20040160299
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 19, 2004
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Publication number: 20020101329
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 1, 2002
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Patent number: 6414585
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: July 2, 2002
    Assignee: Chipscale, Inc.
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Patent number: 6221751
    Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: April 24, 2001
    Assignee: ChipScale, Inc.
    Inventors: Changsheng Chen, Phil P. Marcoux, Wendell B. Sander, James L. Young
  • Patent number: 6051489
    Abstract: A method and apparatus for an electronic component package using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: April 18, 2000
    Assignee: ChipScale, Inc.
    Inventors: James L. Young, Changsheng Chen
  • Patent number: 5910687
    Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: June 8, 1999
    Assignee: ChipScale, Inc.
    Inventors: Changsheng Chen, Phil P. Marcoux, Wendell B. Sander, James L. Young