Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.