Patents by Inventor Changsong Zhang
Changsong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7343470Abstract: Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.Type: GrantFiled: September 26, 2003Date of Patent: March 11, 2008Assignee: Altera CorporationInventors: Juju Joyce, Dan Mansur, David Jefferson, Changsong Zhang, Yi-Wen Lin
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Patent number: 7236411Abstract: A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.Type: GrantFiled: July 21, 2005Date of Patent: June 26, 2007Assignee: Altera CorporationInventors: Rahul Saini, Changsong Zhang, David E. Jefferson
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Patent number: 7138844Abstract: Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.Type: GrantFiled: March 18, 2005Date of Patent: November 21, 2006Assignee: Altera CorporationInventors: Andy L. Lee, Gary Lai, Changsong Zhang, Vaughn Betz, Ryan Fung
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Publication number: 20060208785Abstract: Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.Type: ApplicationFiled: March 18, 2005Publication date: September 21, 2006Inventors: Andy Lee, Gary Lai, Changsong Zhang, Vaughn Betz, Ryan Fung
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Patent number: 7051153Abstract: A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.Type: GrantFiled: May 6, 2002Date of Patent: May 23, 2006Assignee: Altera CorporationInventors: Yi-Wen Lin, Changsong Zhang, David Jefferson, Srinivas Reddy
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Patent number: 6759871Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: GrantFiled: April 22, 2003Date of Patent: July 6, 2004Assignee: Altera CorporationInventors: Triet Nguyen, Changsong Zhang, David Jefferson
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Publication number: 20030201793Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: ApplicationFiled: April 22, 2003Publication date: October 30, 2003Applicant: Altera CorporationInventors: Triet Nguyen, Changsong Zhang, David Jefferson
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Patent number: 6600337Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: GrantFiled: April 26, 2001Date of Patent: July 29, 2003Assignee: Altera CorporationInventors: Triet Nguyen, Changsong Zhang, David Jefferson
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Publication number: 20020003742Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: ApplicationFiled: April 26, 2001Publication date: January 10, 2002Inventors: Triet Nguyen, Changsong Zhang, David Jefferson