Patents by Inventor CHANGWEI YIN

CHANGWEI YIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selected gate driver circuit in memory circuits, and control device and control method thereof
    Patent number: 9583156
    Abstract: A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Changwei Yin, Xiao Zheng
  • SELECTED GATE DRIVER CIRCUIT IN MEMORY CIRCUITS, AND CONTROL DEVICE AND CONTROL METHOD THEREOF
    Publication number: 20170004864
    Abstract: The present disclosure provides a selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 5, 2017
    Inventors: GUANGYAN LUO, HAO NI, CHANGWEI YIN, XIAO ZHENG