Patents by Inventor Chang-Yeong Jeong

Chang-Yeong Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7324395
    Abstract: Semiconductor memory devices and methods of controlling bitlines of such devices in which bitlines of a memory cell array adjacent to an activated memory cell array are precharged to the same voltage.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-yeong Jeong, Sung-Wan Joo, Ji-Hoon Park
  • Patent number: 7224596
    Abstract: Apparatus and methods are provided for repairing semiconductor memory devices having an open bit line sense amplifier architecture with cell array blocks having memory blocks formed of edge sub-blocks, main sub-blocks, dummy sub-blocks. Row defects can be processed using a straight edge block when DQ data are outputted by enabling three word lines such that a repair process for the memory device in an edge sub-block or a dummy sub-block has the same repair efficiency as that of a case where defects occur in a main sub-block.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: May 29, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Yeong Jeong, Hong-Sun Hwang
  • Publication number: 20070047350
    Abstract: Semiconductor memory devices and methods of controlling bitlines of such devices in which bitlines of a memory cell array adjacent to an activated memory cell array are precharged to the same voltage.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 1, 2007
    Inventors: Chang-yeong Jeong, Sung-Wan Joo, Ji-Hoon Park
  • Publication number: 20060098503
    Abstract: Apparatus and methods are provided for repairing semiconductor memory devices having an open bit line sense amplifier architecture with cell array blocks having memory blocks formed of edge sub-blocks, main sub-blocks, dummy sub-blocks. Row defects can be processed using a straight edge block when DQ data are outputted by enabling three word lines such that a repair process for the memory device in an edge sub-block or a dummy sub-block has the same repair efficiency as that of a case where defects occur in a main sub-block.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 11, 2006
    Inventors: Chang-Yeong Jeong, Hong-Sun Hwang