Abstract: The present disclosure provides an integrated circuit, which includes an input stage, a first output stage, and a second output stage. The input stage receives and converts an input clock signal into a first signal and a second signal. The first output stage includes a first inverter and a first buffer circuit. The first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at a first output terminal of the integrated circuit. The second output stage includes a second inverter and a second buffer circuit. The second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at a second output terminal of the integrated circuit. The first output clock signal and the second output clock signal are differential clock signals.

Abstract: A slide rail lock device includes a base unit, a lock member, and a drive member, and is adapted to be disposed on a slide rail unit that includes an outer rail and an inner rail. The base unit includes a base, an inner support frame, and an outer frame that has an outer connection portion and an engagement portion. The engagement portion has an upper plate section, and a plurality of engagement sections that extend downwardly from the upper plate section. The inner support frame cooperates with the base to define a movement slot. The lock member has a lock portion that separably engages one of the engagement sections of the engagement portion. The drive member is operable to move in the movement slot to urge the lock member to rotate so that the lock portion of the lock member is disengaged from the engagement portion.

Abstract: A slide rail lock device includes a base unit, an engagement member, a drive member, and a lock member, and is adapted to be disposed on a slide rail that includes an outer rail and an inner rail. The base unit includes a base, an outer frame, and an inner support frame that cooperates with the base to define a movement slot. The outer frame has an eave portion, an outer connection portion, and an engagement portion. The engagement member separably engages the engagement portion. One end part of the eave portion that is distal to the outer connection portion is formed with a lock groove. The lock member is operable to engage the lock groove. The drive member is operable to move in the movement slot to urge the engagement member to rotate so that the engagement member is disengaged from the engagement portion of the outer frame.

Abstract: A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

Abstract: The present disclosure provides an integrated circuit which includes a first corrector circuit and a second corrector circuit. The first corrector circuit calibrates a first duty cycle of a first clock signal based on an offset calibration code to generate a first output clock signal. The second corrector circuit calibrate a second duty cycle of a second clock signal based on the offset calibration code to generate a second output clock signal. A first trim code includes a first upper portion and a first lower portion, and a second trim code includes a second upper portion and a second lower portion. A first portion of the offset calibration code is an average of the first upper portion and the second upper portion, and a second portion of the offset calibration code is an average of the first lower portion and the second lower portion.

Abstract: The present disclosure provides an integrated circuit, which includes a master circuit and a slave circuit. The master circuit is configured to receive an input clock signal and generate an intermediate clock signal based on a first half and a second half of a first trimming code. The slave circuit is electrically connected to the master circuit and is configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a first half and a second half of a second trimming code. The first trimming code is complementary to the second trimming code.

Abstract: The present disclosure provides an integrated circuit, which includes an input stage, a first output stage, and a second output stage. The input stage receives and converts an input clock signal into a first signal and a second signal. The first output stage includes a first inverter and a first buffer circuit. The first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at a first output terminal of the integrated circuit. The second output stage includes a second inverter and a second buffer circuit. The second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at a second output terminal of the integrated circuit. The first output clock signal and the second output clock signal are differential clock signals.

Abstract: A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

Abstract: A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

Abstract: The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

Abstract: A display apparatus including a display panel is provided. The display panel has a plurality of display blocks, wherein each display block includes a light conversion circuit, a pixel array, and a data voltage selection circuit. The light conversion circuit receives the light pulse signal and has a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled between a system high voltage and a system low voltage, and the pull-up circuit and the pull-down circuit output the system high voltage or system low voltage according to the light pulse signal to form a voltage pulse signal. The data voltage selection circuit is coupled to the light conversion circuit and the pixel array and receives an AC waveform voltage to supply a data signal to the pixel array according to the voltage pulse signal.

Abstract: A display apparatus including a display panel is provided. The display panel has a plurality of display blocks, wherein each display block includes a light conversion circuit, a pixel array, and a data voltage selection circuit. The light conversion circuit receives the light pulse signal and has a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled between a system high voltage and a system low voltage, and the pull-up circuit and the pull-down circuit output the system high voltage or system low voltage according to the light pulse signal to form a voltage pulse signal. The data voltage selection circuit is coupled to the light conversion circuit and the pixel array and receives an AC waveform voltage to supply a data signal to the pixel array according to the voltage pulse signal.

Abstract: A display apparatus including a display panel is provided. The display panel has a plurality of display blocks, wherein each display block includes a light conversion circuit, a pixel array, and a data voltage selection circuit. The light conversion circuit receives the light pulse signal and has a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled between a system high voltage and a system low voltage, and the pull-up circuit and the pull-down circuit output the system high voltage or system low voltage according to the light pulse signal to form a voltage pulse signal. The data voltage selection circuit is coupled to the light conversion circuit and the pixel array and receives an AC waveform voltage to supply a data signal to the pixel array according to the voltage pulse signal.

Abstract: A pixel array structure includes a plurality of scanning lines and a plurality of pixel blocks. Each pixel block includes a plurality of data lines, a plurality of pixel units, a wireless receiving unit, and a position selection unit. The plurality of pixel units is arranged in an array form, and each pixel unit is coupled to one of the plurality of scanning lines and one of the plurality of data lines. The wireless receiving unit receives a data signal in a wireless manner. The position selection unit transmits the data signal to one of the plurality of data lines according to a position selection signal.

Abstract: A display apparatus including a display panel is provided. The display panel has a plurality of display blocks, wherein each display block includes a light conversion circuit, a pixel array, and a data voltage selection circuit. The light conversion circuit receives the light pulse signal and has a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled between a system high voltage and a system low voltage, and the pull-up circuit and the pull-down circuit output the system high voltage or system low voltage according to the light pulse signal to form a voltage pulse signal. The data voltage selection circuit is coupled to the light conversion circuit and the pixel array and receives an AC waveform voltage to supply a data signal to the pixel array according to the voltage pulse signal.

Abstract: A pixel array structure includes a plurality of scanning lines and a plurality of pixel blocks. Each pixel block includes a plurality of data lines, a plurality of pixel units, a wireless receiving unit, and a position selection unit. The plurality of pixel units is arranged in an array form, and each pixel unit is coupled to one of the plurality of scanning lines and one of the plurality of data lines. The wireless receiving unit receives a data signal in a wireless manner. The position selection unit transmits the data signal to one of the plurality of data lines according to a position selection signal.

Abstract: A light guide plate including a first substrate, a second substrate opposite to the first substrate, a plurality of first microstructures, a plurality of second microstructures, and a plurality of third microstructures is provided. The first substrate has a light emitting surface, a first bottom surface, and a light incidence surface. The second substrate has a top surface and a second bottom surface. The top surface is located between the first substrate and the second bottom surface. The first microstructures and the second microstructures are disposed on the light emitting surface and the second bottom surface respectively and extend along a first direction parallel to the light incidence surface respectively. The third microstructures are connected between the first bottom surface and the top surface and extend along a second direction perpendicular to the light incidence surface respectively. A light source module is also provided.

Abstract: A quasi-crystal organic light-emitting display panel including a first electrode layer, an organic light-emitting layer, a second electrode layer, a buffer layer, a 10-fold quasi-crystal layer and a package cover is provided. The organic light-emitting layer is located on the first electrode layer. The second electrode layer is located on the organic light-emitting layer. The buffer layer is located on the second electrode layer. The 10-fold quasi-crystal layer is located on the buffer layer. The package cover is located on the 10-fold quasi-crystal layer. A method for simulating optical efficiency of the quasi-crystal organic light-emitting display panel is also provided.

Abstract: A light guide plate including a first substrate, a second substrate opposite to the first substrate, a plurality of first microstructures, a plurality of second microstructures, and a plurality of third microstructures is provided. The first substrate has a light emitting surface, a first bottom surface, and a light incidence surface. The second substrate has a top surface and a second bottom surface. The top surface is located between the first substrate and the second bottom surface. The first microstructures and the second microstructures are disposed on the light emitting surface and the second bottom surface respectively and extend along a first direction parallel to the light incidence surface respectively. The third microstructures are connected between the first bottom surface and the top surface and extend along a second direction perpendicular to the light incidence surface respectively. A light source module is also provided.

Abstract: A quasi-crystal organic light-emitting display panel including a first electrode layer, an organic light-emitting layer, a second electrode layer, a buffer layer, a 10-fold quasi-crystal layer and a package cover is provided. The organic light-emitting layer is located on the first electrode layer. The second electrode layer is located on the organic light-emitting layer. The buffer layer is located on the second electrode layer. The 10-fold quasi-crystal layer is located on the buffer layer. The package cover is located on the 10-fold quasi-crystal layer. A method for simulating optical efficiency of the quasi-crystal organic light-emitting display panel is also provided.