Abstract: An image sensor includes a first semiconductor substrate, a photoelectric conversion region in the first semiconductor substrate, and a buried insulating film on the first semiconductor substrate. The buried insulating film covers a first region of the first semiconductor substrate and exposes a second region of the first semiconductor substrate. The sensor includes a second semiconductor substrate on the buried insulating film, an operating gate structure defining a first channel of a first conductive type in the second semiconductor substrate, and a transfer gate structure defining a second channel of a second conductive type different from the first conductive type in the second region of the first semiconductor substrate.

Abstract: A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).

Abstract: An image processing apparatus and image processing method according to the present disclosure are characterized to obtain N number of image data regarding a same object, each N number of image data consisting of a plurality of pixels; remove noise data of among N number of pixel data regarding pixels in a same location, from the N number of image data; and generate an image of the object using data excluding the noise data.

Abstract: A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.

Abstract: According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

Abstract: A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).

Abstract: A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.

Abstract: An image processing apparatus and image processing method according to the present disclosure are characterized to obtain N number of image data regarding a same object, each N number of image data consisting of a plurality of pixels; remove noise data of among N number of pixel data regarding pixels in a same location, from the N number of image data; and generate an image of the object using data excluding the noise data.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.

Abstract: According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

Abstract: A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described.

Abstract: A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described.