Patents by Inventor CHANGYUP PARK
CHANGYUP PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240065118Abstract: Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.Type: ApplicationFiled: December 20, 2022Publication date: February 22, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Hajun SUNG, Youngjae Kang, Changyup Park, Kiyeon Yang, Wooyoung Yang, Changseung Lee, Minwoo Choi
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Publication number: 20240057347Abstract: A memory element includes a substrate, a first electrode formed on the substrate, a phase-change heterolayer formed on the first electrode and electrically connected to the first electrode, and a second electrode formed on the phase-change heterolayer, wherein the phase-change heterolayer includes one or more confinement material layers and one or more phase-change material layers, and the confinement material layer includes a metal chalcogenide film.Type: ApplicationFiled: July 7, 2023Publication date: February 15, 2024Applicants: Samsung Electronics Co., Ltd., UIF (University Industry Foundation), Yonsei UniversityInventors: Wooyoung YANG, Hyungjun Kim, Hajun Sung, Kiyeon Yang, Changseung Lee, Changyup Park, Seung-min Chung, Sangyoon Lee, Inkyu Sohn
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Publication number: 20230301218Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGedSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1?a?18, 13?b?26, 15?c?30, 35?d?55, 0.1?e?8, 0.1?f?8, and a+b+c+d+e+f=100.Type: ApplicationFiled: March 10, 2023Publication date: September 21, 2023Inventors: Wonjun PARK, Chungman KIM, Dongho AHN, Changyup PARK
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Publication number: 20230230832Abstract: A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of Ge2Sb2+aTe5+b, in which a and b satisfy the following relations: ?0.2<a<0.2 and ?0.5<b<0.5.Type: ApplicationFiled: January 10, 2023Publication date: July 20, 2023Applicant: Industry Academy Cooperation Foundation Of Sejong UniversityInventors: Donggeon GU, Won-Jun LEE, Changyup PARK, Dongho AHN, Yewon KIM, Kwonyoung KIM, Okhyeon KIM
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Publication number: 20230232640Abstract: A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.Type: ApplicationFiled: September 9, 2022Publication date: July 20, 2023Inventors: JINWOO LEE, DONGHO AHN, DONGGEON GU, WONJUN PARK, CHANGYUP PARK
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Patent number: 11600776Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.Type: GrantFiled: September 25, 2020Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaeho Jung, Kyoung Sun Kim, Jeonghee Park, Jiho Park, Changyup Park
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Patent number: 11574956Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.Type: GrantFiled: May 7, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jiho Park, Kwangmin Park, Wonjun Park, Jeonghee Park, Changyup Park, Hwasung Chae
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Patent number: 11482670Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 ?s to about 54 ?s.Type: GrantFiled: June 23, 2020Date of Patent: October 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiho Park, Kwangmin Park, Jeonghee Park, Changyup Park, Sukhwan Chung
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Publication number: 20220085105Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.Type: ApplicationFiled: May 7, 2021Publication date: March 17, 2022Inventors: Jiho Park, Kwangmin Park, Wonjun Park, Jeonghee Park, Changyup Park, Hwasung Chae
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Patent number: 11037992Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.Type: GrantFiled: September 11, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeonghee Park, Dongho Ahn, Changyup Park, Zhe Wu
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Patent number: 11017989Abstract: Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.Type: GrantFiled: September 11, 2018Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiho Park, Jeonghee Park, Changyup Park
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Publication number: 20210104669Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 ?s to about 54 ?s.Type: ApplicationFiled: June 23, 2020Publication date: April 8, 2021Inventors: JIHO PARK, KWANGMIN PARK, JEONGHEE PARK, CHANGYUP PARK, SUKHWAN CHUNG
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Publication number: 20210013410Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jaeho JUNG, KYOUNG SUN KIM, JEONGHEE PARK, JIHO PARK, Changyup PARK
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Patent number: 10892410Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.Type: GrantFiled: July 2, 2019Date of Patent: January 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jeonghee Park, Jiho Park, Changyup Park, Dongho Ahn
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Patent number: 10818839Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.Type: GrantFiled: October 2, 2018Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaeho Jung, Kyoung Sun Kim, Jeonghee Park, Jiho Park, Changyup Park
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Publication number: 20200227475Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.Type: ApplicationFiled: September 11, 2019Publication date: July 16, 2020Inventors: Jeonghee PARK, Dongho AHN, Changyup PARK, Zhe WU
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Publication number: 20200075850Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.Type: ApplicationFiled: July 2, 2019Publication date: March 5, 2020Inventors: JEONGHEE PARK, JIHO PARK, CHANGYUP PARK, DONGHO AHN
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Patent number: 10566530Abstract: Disclosed is a method of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, the mold layer having a hole exposing a portion of the substrate, forming a phase transition layer with a void, in the hole, and thermally treating the phase transition layer to remove the void from the phase transition layer. The thermal treating of the phase transition layer may include heating the substrate to a first temperature to form a diffusion layer in the phase transition layer, and the first temperature may be lower than or equal to 55% of a melting point of the phase transition layer.Type: GrantFiled: October 25, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changyup Park, Jeonghee Park, Jaeho Jung
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Publication number: 20190288204Abstract: Disclosed is a method of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, the mold layer having a hole exposing a portion of the substrate, forming a phase transition layer with a void, in the hole, and thermally treating the phase transition layer to remove the void from the phase transition layer. The thermal treating of the phase transition layer may include heating the substrate to a first temperature to form a diffusion layer in the phase transition layer, and the first temperature may be lower than or equal to 55% of a melting point of the phase transition layer.Type: ApplicationFiled: October 25, 2018Publication date: September 19, 2019Inventors: Changyup PARK, JEONGHEE PARK, Jaeho JUNG
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Publication number: 20190288203Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.Type: ApplicationFiled: October 2, 2018Publication date: September 19, 2019Inventors: Jaeho JUNG, KYOUNG SUN KIM, JEONGHEE PARK, JIHO PARK, Changyup PARK