Abstract: A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

Abstract: A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

Abstract: A backward diode including a heterostructure consisting of a first layer of InAs and second layer of GaSb or InGaSb with an interface layer consisting of an aluminum antimonide compound is presented. It is also disclosed that the presence of AlSb in the interface enhances the highly desirable characteristic of nonlinear current-voltage (I-V) curve near zero bias. The backward diode is useful in radio frequency detection and mixing. The interface layer may be one or more layers in thickness, and may also have a continuously graded AlGaSb layer with a varying Al concentration in order to enhance the nonlinear I-V curve characteristic near zero bias.

Abstract: A process is provided for fabricating MODFET's in group III nitride compound semiconductors. The process precedes isolation of the MODFET structure with the use of e-beam lithography to define very narrow (e.g., .about.0.25 micrometer) gates which enhance transistor microwave cut-off frequency. Because these compound semiconductors resist chemical etchants, isolation is accomplished by etching with reactive ions to form an isolation mesa having a vertical mesa sidewall. To improve breakdown, the mesa sidewall is covered with a passivation layer prior to deposition of a gate feed that contacts the gate. To reduce parasitic gate capacitance, the gate feed is spaced from a narrow edge of the transistor's two-dimensional electron gas.

Abstract: A process is provided for fabricating MODFET's in group III nitride compound semiconductors. The process precedes isolation of the MODFET structure with the use of e-beam lithography to define very narrow (e.g., .about.0.25 micrometer) gates which enhance transistor microwave cut-off frequency. Because these compound semiconductors resist chemical etchants, isolation is accomplished by etching with reactive ions to form an isolation mesa having a vertical mesa sidewall. To improve breakdown, the mesa sidewall is covered with a passivation layer prior to deposition of a gate feed that contacts the gate. To reduce parasitic gate capacitance, the gate feed is spaced from a narrow edge of the transistor's two-dimensional electron gas.

Abstract: The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample to repair broken bonds and crystalline defects and to move implanted species atoms from interstitial to substitutional sites. An optional third step deposits a dummy layer on the sample surface prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer than is attainable without the dummy layer and to inhibit species atoms from leaving the sample during high-temperature processing steps that follow.

Abstract: A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.