Patents by Inventor Chanh Tran
Chanh Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870982Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: GrantFiled: October 3, 2016Date of Patent: January 16, 2018Assignee: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Publication number: 20170098595Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: ApplicationFiled: October 3, 2016Publication date: April 6, 2017Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Patent number: 9466568Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: GrantFiled: April 9, 2015Date of Patent: October 11, 2016Assignee: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Publication number: 20150221589Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: ApplicationFiled: April 9, 2015Publication date: August 6, 2015Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Patent number: 9006907Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: GrantFiled: May 28, 2013Date of Patent: April 14, 2015Assignee: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Publication number: 20130320560Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: ApplicationFiled: May 28, 2013Publication date: December 5, 2013Applicant: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Patent number: 8458426Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.Type: GrantFiled: January 19, 2007Date of Patent: June 4, 2013Assignee: Rambus Inc.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, Nancy D. Dillon
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Patent number: 8086812Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.Type: GrantFiled: August 17, 2006Date of Patent: December 27, 2011Assignee: Rambus Inc.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, John B. Dillon, Nancy D. Dillon, legal representative
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Publication number: 20070257693Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.Type: ApplicationFiled: May 3, 2006Publication date: November 8, 2007Inventors: Bret Stott, Philip Yeung, John Brooks, Benedict Lau, Chanh Tran, Eugene Ho
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Publication number: 20070118711Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: RAMBUS INC.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, John Dillon, Nancy Dillon
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Publication number: 20070011426Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.Type: ApplicationFiled: August 17, 2006Publication date: January 11, 2007Applicant: Rambus Inc.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, John Dillon, Nancy Dillon
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Patent number: 7124270Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.Type: GrantFiled: March 11, 2005Date of Patent: October 17, 2006Assignee: Rambus Inc.Inventors: Nancy D. Dillon, legal representative, Kevin Donnelly, Mark Johnson, Chanh Tran, John B. Dillon, deceased
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Publication number: 20060188051Abstract: A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.Type: ApplicationFiled: April 18, 2006Publication date: August 24, 2006Inventors: Kevin Donnelly, Pak Chau, Mark Horowitz, Thomas Lee, Mark Johnson, Benedict Lau, Leung Yu, Bruno Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Tran, Donald Stark, Nhat Nguyen
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Patent number: 7065622Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.Type: GrantFiled: February 15, 2005Date of Patent: June 20, 2006Assignee: Rambus Inc.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, Nancy D. Dillon, legal representative, John B. Dillon, deceased
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Patent number: 7010658Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.Type: GrantFiled: October 31, 2003Date of Patent: March 7, 2006Assignee: Rambus Inc.Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, Nancy D. Dillon, legal representative, John B. Dillon, deceased
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Publication number: 20050160247Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.Type: ApplicationFiled: March 11, 2005Publication date: July 21, 2005Inventors: John Dillon, Nancy Dillon, Kevin Donnelly, Mark Johnson, Chanh Tran
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Publication number: 20050149685Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, John Dillon, Nancy Dillon
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Publication number: 20050057275Abstract: Disclosed is an output driver having an output port for outputting a data signal, a level shifter for driving a current to the output port in response to a current control input, an adjustable impedance controller for generating an impedance adjustment signal; an output impedance compensator for adjusting the impedance of the level shifter in accordance with the impedance adjustment signal and in accordance with a reference voltage, and a tracking circuit, including a process and temperature monitor responsive to manufacturing process and temperature variations of the output driver, a frequency monitor responsive to the frequency of an input clock signal, and a voltage supply monitor responsive to an internal power supply voltage. The process and temperature monitor, frequency monitor and voltage supply monitor are interconnected so as to generate the reference voltage.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Inventors: Huy Ngyuen, Chanh Tran
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Patent number: 6819137Abstract: A technique for voltage level shifting in input circuitry is disclosed. In one exemplary embodiment, the technique may be realized as a method for voltage level shifting input signals. This method may comprise receiving first and second input signals having first and second voltage levels, respectively, and then differentially amplifying the first and second input signals so as to generate first and second amplified voltage signals having first and second amplified voltage levels, respectively, wherein the first and second amplified voltage signals are substantially complementary. This method may then comprise reducing the first and second amplified voltage levels of the first and second amplified voltage signals so as to generate first and second level shifted amplified voltage signals having first and second level shifted amplified voltage levels, respectively.Type: GrantFiled: September 10, 2002Date of Patent: November 16, 2004Assignee: Rambus Inc.Inventors: Yueyong Wang, Jade Kizer, Chanh Tran, Benedict Lau
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Patent number: 6809569Abstract: A circuit includes a first node having a first variable voltage and a second node having a second variable voltage. A clock signal generates the first variable and second variable voltages. A first transistor is coupled to the first node and provides a first current responsive to a first control voltage being applied to the first transistor gate. A second transistor is coupled to the second node and provides a second current responsive to a second control voltage being applied to the second transistor gate. A first control circuit is coupled to the first transistor gate and the second node. The first control circuit provides the first control voltage responsive to the first variable voltage. A second control circuit is coupled to the second transistor gate and the first node. The second control circuit provides the second control voltage responsive to the second variable voltage. The first and second currents are used to provide a duty cycle correction signal.Type: GrantFiled: February 28, 2002Date of Patent: October 26, 2004Assignee: Rambus Inc.Inventors: Yueyong Wang, Chanh Tran