Abstract: The present disclosure provides a compound of Chemical Formula (1) or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same: wherein X, Z, R1 and R2 are as defined in the specification. The compound of Chemical Formula (1) or pharmaceutically acceptable salt thereof acts as a positive allosteric modulator of metabotropic glutamate receptor subtype 5 (mGluR5), thereby being useful in the prevention or treatment of disorder mediated by glutamate dysfunction and mGluR5.

Abstract: The present invention relates to an electrode for a fuel cell, comprising a non-platinum catalyst and a graphene layered structure, and a membrane-electrode assembly comprising the same and, more specifically, to a membrane-electrode assembly for a fuel cell and a fuel cell comprising the same, which implement excellent electrode efficiency through relatively inexpensive transition metals while not using platinum, by stacking alternately with a graphene layer, a catalyst layer comprising both a non-platinum catalyst complex including a carbon support, nitrogen, and non-platinum transition metal, and a conductive polymer.

Abstract: A power supply system may include a target device and an adapter. The target device may include an adapter connection switch that receives adapter recognition information to form a connection with the adapter, a voltage detection unit that receives an output voltage from an adapter, and a voltage-change-requesting unit that outputs a voltage to request a voltage change based on information on the output voltage from the adapter. The adapter may include a device information recognition unit that receives the voltage to request a voltage change, and an output-voltage-changing unit that changes the output voltage based on the voltage to request a voltage change.

Abstract: A coil component includes a body, a coil portion disposed in the body and having first and second lead-out portions exposed to at least one surface of the body to be spaced apart from each other, first and second external electrodes disposed on the at least one surface of the body to be spaced apart from each other, and respectively connected to the first and second lead-out portions, a dielectric layer disposed on a surface of the body, and a third external electrode disposed on the surface of the body having the dielectric layer disposed thereon to be spaced apart from each of the first and second external electrodes, and covering the dielectric layer.

Abstract: A coil component includes a body having a core, a coil portion disposed in the body and having a central portion in which the core is disposed, a first external electrode and a second external electrode, each connected to the coil portion, a third external electrode spaced apart from each of the first and second external electrodes, and a noise removal portion disposed to at least partially surround the coil portion between a surface of the body and the core and having both end portions, each connected to the third external electrode.

Abstract: The present disclosure provides a compound of Chemical Formula (1) or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same: wherein X, Z, R1 and R2 are as defined in the specification. The compound of Chemical Formula (1) or pharmaceutically acceptable salt thereof acts as a positive allosteric modulator of metabotropic glutamate receptor subtype 5 (mGluR5), thereby being useful in the prevention or treatment of disorder mediated by glutamate dysfunction and mGluR5.

Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.

Abstract: A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active region, an insulating layer pattern on the substrate and including a hole corresponding with the first active region, a DC conductive pattern in the hole, connected to the first active region, and buried in the substrate, a bit line connected to the DC conductive pattern and including a first bit line conductive pattern contacting the DC conductive pattern and covering a top surface of the insulating layer pattern, and a gate insulating layer and a gate electrode structure on the second active region, the gate electrode structure including a gate conductive pattern and a first gate electrode conductive pattern, the first gate electrode conductive pattern including a same material as the first bit line conductive pattern.

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.

Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.

Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.