Abstract: A thermally adhesive fiber web implemented by including the steps of: (1) preparing respectively a first spinning solution in which a support component and a second spinning solution in which a thermally adhesive component; (2) performing electrospinning such that the first spinning solution is discharged to a portion of the end surface of a discharge port and the second spinning solution is discharged to the remaining portion, thereby accumulating side-by-side type thermally adhesive composite fibers having a diameter of less than 1 ?m; and (3) applying heat to the accumulated side-by-side type thermally adhesive composite fibers. The thermally adhesive fiber web enables easy interfacial bonding to a heterogeneous material with a different material and structural specification and prevents pores formed in an initial stage from being closed during thermal bonding.

Abstract: The present invention relates to a method for dipping an adhesive material, and the method for dipping an adhesive material includes dipping an adhesive material onto a first dipping stamp, transferring the adhesive material, which is dipped onto the first dipping stamp, to a target substrate, and transferring a device to the target substrate, to which the adhesive material is transferred.

Abstract: A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.

Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.

Abstract: A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active region, an insulating layer pattern on the substrate and including a hole corresponding with the first active region, a DC conductive pattern in the hole, connected to the first active region, and buried in the substrate, a bit line connected to the DC conductive pattern and including a first bit line conductive pattern contacting the DC conductive pattern and covering a top surface of the insulating layer pattern, and a gate insulating layer and a gate electrode structure on the second active region, the gate electrode structure including a gate conductive pattern and a first gate electrode conductive pattern, the first gate electrode conductive pattern including a same material as the first bit line conductive pattern.

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.

Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.

Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.