Patents by Inventor Chantal Auricchio
Chantal Auricchio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798630Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.Type: GrantFiled: August 20, 2021Date of Patent: October 24, 2023Assignee: STMicroelectronics S.r.l.Inventors: Marcella Carissimi, Fabio Enrico Carlo Disegni, Chantal Auricchio, Cesare Torti, Davide Manfre', Laura Capecchi, Emanuela Calvetti, Stefano Zanchi
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Patent number: 11798603Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: GrantFiled: February 27, 2023Date of Patent: October 24, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Vivek Tyagi, Vikas Rana, Chantal Auricchio, Laura Capecchi
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Publication number: 20230206971Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Vivek TYAGI, Vikas RANA, Chantal AURICCHIO, Laura CAPECCHI
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Patent number: 11615823Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: GrantFiled: December 3, 2021Date of Patent: March 28, 2023Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Vivek Tyagi, Vikas Rana, Chantal Auricchio, Laura Capecchi
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Publication number: 20220165317Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: ApplicationFiled: December 3, 2021Publication date: May 26, 2022Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Vivek TYAGI, Vikas RANA, Chantal AURICCHIO, Laura CAPECCHI
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Publication number: 20220068395Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.Type: ApplicationFiled: August 20, 2021Publication date: March 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Marcella CARISSIMI, Fabio Enrico Carlo DISEGNI, Chantal AURICCHIO, Cesare TORTI, Davide MANFRE', Laura CAPECCHI, Emanuela CALVETTI, Stefano ZANCHI
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Patent number: 11205462Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: GrantFiled: September 2, 2020Date of Patent: December 21, 2021Assignees: STMicroelectronics International N.V., STMicroelectronics S.R.L.Inventors: Vivek Tyagi, Vikas Rana, Chantal Auricchio, Laura Capecchi
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Publication number: 20210074340Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.Type: ApplicationFiled: September 2, 2020Publication date: March 11, 2021Inventors: Vivek TYAGI, Vikas RANA, Chantal AURICCHIO, Laura CAPECCHI
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Patent number: 10755777Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.Type: GrantFiled: October 24, 2018Date of Patent: August 25, 2020Assignee: STMicroelectronics S.R.L.Inventors: Marcella Carissimi, Marco Pasotti, Chantal Auricchio
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Publication number: 20190130970Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.Type: ApplicationFiled: October 24, 2018Publication date: May 2, 2019Inventors: Marcella Carissimi, Marco Pasotti, Chantal Auricchio
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Patent number: 10068643Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.Type: GrantFiled: February 1, 2017Date of Patent: September 4, 2018Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Marco Pasotti, Marcella Carissimi, Rajat Kulshrestha, Chantal Auricchio
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Publication number: 20170178722Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.Type: ApplicationFiled: February 1, 2017Publication date: June 22, 2017Inventors: Marco Pasotti, Marcella Carissimi, Rajat Kulshrestha, Chantal AURICCHIO
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Patent number: 9613692Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.Type: GrantFiled: December 16, 2015Date of Patent: April 4, 2017Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Marco Pasotti, Marcella Carissimi, Rajat Kulshrestha, Chantal Auricchio
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Patent number: 7088135Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.Type: GrantFiled: January 20, 2004Date of Patent: August 8, 2006Assignee: STMicroelectronics S.r.l.Inventors: Chantal Auricchio, Michele Borgatti, Pier Luigi Rolandi
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Publication number: 20040233736Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.Type: ApplicationFiled: January 20, 2004Publication date: November 25, 2004Applicant: STMicroelectronics S.r.l.Inventors: Chantal Auricchio, Michele Borgatti, Pier Luigi Rolandi