Abstract: Provided are an apparatus and a method using a convolutional neural network (CNN) including a plurality of convolution layers in the field of artificial intelligence (AI) systems and applications thereof. A computing apparatus using a CNN including a plurality of convolution layers includes a memory storing one or more instructions; and one or more processors configured to execute the one or more instructions stored in the memory to obtain input data; identify a filter for performing a convolution operation with respect to the input data, on one of the plurality of convolution layers; identify a plurality of sub-filters corresponding to different filtering regions within the filter; provide a plurality of feature maps based on the plurality of sub-filters; and obtain output data, based on the plurality of feature maps.

Abstract: An electronic device and a method for controlling the same include inputting an input image into an artificial intelligence model, acquiring a feature map for the input image, converting the feature map through a lookup table corresponding to the feature map, and storing the converted feature map by compressing the feature map through a compression mode corresponding to the feature map.

Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.

Abstract: An electronic device and a method for managing memory thereof are disclosed. According to an embodiment of the present disclosure, a method for an electronic device to manage memory, comprising: determining whether a physical address mapped to a virtual address is consecutive with respect to at least two entries belonging to a plurality of entries having virtual addresses and physical addresses mapped and including a consecutive virtual address; merging entries in which the virtual address and the physical address are consecutive into one entry if, as a result of the determination, the physical addresses of the at least entries are consecutive; and storing the merged entry in first memory.

Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.

Abstract: An electronic device, an on-chip memory and a method of operating the on-chip memory are disclosed. The on-chip memory including an on-chip memory comprises: a plurality of design Intellectual Property (IPs), a memory that includes a storage area and a processor connected to the memory, wherein the processor is configured to monitor a memory traffic of at least one IP among the plurality of design IPs, and control usage of a storage area based on a result of the monitoring. According to the electronic device, the on-chip memory and the method of operating the on-chip memory of the present disclosure, in an AP-CP one chip structure, a stable communication is secured, memory latency is secured for a code required to process a real time of a CP, and in the AP-CP one chip structure, a communication bandwidth is improved.