Abstract: An optical device package includes a substrate, a light emitting device, a light detecting device, one or more electronic chips, a clear encapsulation layer and a patterned reflective layer. The substrate has a surface. The light emitting device is disposed on the surface of the substrate, the light detecting device is disposed on the surface of the substrate, and the light emitting device and the light detecting device have a gap. The one or more electronic chips are at least partially embedded in the substrate, and electrically connected to the light emitting device and the light detecting device. The clear encapsulation layer is disposed on the surface of the substrate and encapsulates the light emitting device and the light detecting device. The patterned reflective layer is disposed on an upper surface of the clear encapsulation layer and at least overlaps the gap between the light emitting device and the light detecting device in a projection direction perpendicular to the surface of the substrate.

Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a substrate having a first face and an opposing second face, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; and a first shielding member covering the first semiconductor component and a first group of the plurality of connectors, while exposing a second group of the plurality of connectors.

Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.

Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by physical vapor deposition on the backside of the bowed semiconductor substrate in regions to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve sputtering material onto a backside of a substrate using a shadow mask or by using more than one target and rotating the semiconductor substrate being sputtering operations.

Abstract: An optical device package includes a substrate, a light emitting device, a light detecting device, one or more electronic chips, a clear encapsulation layer and a patterned reflective layer. The substrate has a surface. The light emitting device is disposed on the surface of the substrate, the light detecting device is disposed on the surface of the substrate, and the light emitting device and the light detecting device have a gap. The one or more electronic chips are at least partially embedded in the substrate, and electrically connected to the light emitting device and the light detecting device. The clear encapsulation layer is disposed on the surface of the substrate and encapsulates the light emitting device and the light detecting device. The patterned reflective layer is disposed on an upper surface of the clear encapsulation layer and at least overlaps the gap between the light emitting device and the light detecting device in a projection direction perpendicular to the surface of the substrate.

Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by physical vapor deposition on the backside of the bowed semiconductor substrate in regions to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve sputtering material onto a backside of a substrate using a shadow mask or by using more than one target and rotating the semiconductor substrate being sputtering operations.

Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: A seed layer of aluminum is deposited over a wafer. A layer of photoresist material is deposited over the seed layer of aluminum. The photoresist material is patterned and developed to expose portions of the seed layer of aluminum through openings in the photoresist material. An electrochemical transformation process is performed on the wafer to electrochemically transform the portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide (AAO). The AAO includes a pattern of holes that extend through the AAO to expose areas of the top surface of the wafer beneath the seed layer of aluminum. The photoresist material is removed from the wafer. The wafer is exposed to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the AAO.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.