Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: Apparatus, systems and methods for irrigating lands are disclosed. In one example, an irrigation system is disclosed. The irrigation system includes a gate and a microcontroller unit (MCU). The gate is configured for adjusting a water flow for irrigating a piece of land. The MCU is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.

Abstract: The method for using semiconductor intelligence line of the invention, which is to set the semiconductor intelligence line on the drain source voltage axis of the first semiconductor output characteristic, has a gate voltage setting, which indicates the function of limiting the application limit of the drain source current on the output characteristic.

Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

Abstract: The method for using semiconductor intelligence line of the invention, which is to set the semiconductor intelligence line on the drain source voltage axis of the first semiconductor output characteristic, has a gate voltage setting, which indicates the function of limiting the application limit of the drain source current on the output characteristic.

Abstract: This invention is related to a universal cell, the universal cell includes a positive terminal, a first conductor, a voltage balance circuit, a positive tab, an electrode spiral, a negative tab, a negative terminal, and battery container. The universal cell utilizes a characteristic of voltage balance circuit that the universal cell can be connected with another universal cell in parallel without generating a current-circulation loss at an idle state, a charge state, or a discharge state.

Abstract: The present invention related to a cell interface. The cell interface includes four diode D1 to D4. A first terminal connected to a voltage terminal of first cell; a second terminal connected to a voltage terminal of second cell; and a third terminal connected to an external voltage terminal of an external electric circuit, another external voltage terminal connected to another voltage terminal of first cell and second cell. The cell interface can prevent from occurring loop current in parallel cell.

Abstract: This invention relates is a Hall effect transformer, which include: Hall effect device, insulation layer and semiconductor, place the insulator layer between the Hall effect device and semiconductor used as an isolated, when AC current flow through the AC capacitors and Hall effect device, semiconductor corresponds to get both terminals of the AC voltage, and AC power transmission purposes.

Abstract: The invention related in cell parallel device is a circuit of SCR S1 to S4, comprises: a first terminal connected T1 to positive voltage terminal of first cell E1; a second terminal T2 connected to positive voltage terminal of second cell E2; and a third terminal T3 connected to voltage positive terminal of charge element CD or load LD, and trigger element TE connected between gate and anode of the SCR S1 to S4, the negative voltage terminal of charge element CD or load LD connected to negative voltage terminal of first cell E1 and second cell E2, can be not occur loop current in cells parallel circuit.

Abstract: The switch in this invention is connected in series with two field effect transistor, comprises: the source S1 of first N-channel FET F1 and the source S2 of second N-channel FET F2 are directly connected together form a third terminal VA, the gate G1 of first N-channel FET F1 and the gate G2 of second N-channel FET F2 are connected together form a control terminal GA, the drain D1 of first N-channel FET F1 form a first terminal D1, the drain D2 of second N-channel FET F2 form a second terminal D2, the body diode DA of first N-channel FET F1 and the body diode DB of second N-channel FET F2, are back-to-back series connected together, the right side equivalent circuit F are first N-channel FET F1 and second N-channel FET F2 equivalent circuit, form a switch F of the present invention.

Abstract: The invention related in cell interface is a circuit of diode D1 to D4, comprises: a first terminal connected to positive voltage terminal of first cell E1; a second terminal connected to positive voltage terminal of second cell E2; and a third terminal connected to external positive terminal VP, the external negative voltage terminal VN connected to negative voltage terminal of first cell E1 and second cell E2, can be not occur loop current in parallel circuit.

Abstract: An increase source to drain breakdown voltage vertical channel transistors device having a structure that is similar to that of a conventional metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate and a body. According the N+N? and P+P? junction theory of semiconductor, add to N? junction between the source N+ junction to P junction of N-Channel MOSFET; add to P? junction between the source P+ junction to n junction of P-Channel MOSFET; With the proposed MOSFET of which the source to drain breakdown voltage are increase may be achieved.

Abstract: A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off.

Abstract: This invention relates in Synchronous Rectifier Circuits, comprises: AC input terminal, switch, driving circuit, protect opposite current circuit and a load, to improved conventional Synchronous Rectifier Circuits, can be achieve rectify function.

Abstract: A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off.

Abstract: A rectifier driving circuit of the present invention, has a first driving element and a second driving element, switching element comprises a FET, a first driving element comprises the voltage drop resistor, a second driving element comprises the series-connected circuit of the diodes, the driving element for driving a FET, may be achieved rectify function.

Abstract: A single-ended forward converter of the present invention, has first and second switching element comprises a pair Lus N-Channel FET, a first driving circuit comprises the series-connected circuit of the first voltage drop resistor and first zener diode for driving first Lus N-Channel FET, a second driving circuit comprises the series-connected circuit of the second voltage drop resistor and second zener diode for driving second Lus N-Channel FET.