Abstract: The method for using semiconductor intelligence line of the invention, which is to set the semiconductor intelligence line on the drain source voltage axis of the first semiconductor output characteristic, has a gate voltage setting, which indicates the function of limiting the application limit of the drain source current on the output characteristic.

Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

Abstract: The method for using semiconductor intelligence line of the invention, which is to set the semiconductor intelligence line on the drain source voltage axis of the first semiconductor output characteristic, has a gate voltage setting, which indicates the function of limiting the application limit of the drain source current on the output characteristic.

Abstract: This invention is related to a universal cell, the universal cell includes a positive terminal, a first conductor, a voltage balance circuit, a positive tab, an electrode spiral, a negative tab, a negative terminal, and battery container. The universal cell utilizes a characteristic of voltage balance circuit that the universal cell can be connected with another universal cell in parallel without generating a current-circulation loss at an idle state, a charge state, or a discharge state.

Abstract: The present invention related to a cell interface. The cell interface includes four diode D1 to D4. A first terminal connected to a voltage terminal of first cell; a second terminal connected to a voltage terminal of second cell; and a third terminal connected to an external voltage terminal of an external electric circuit, another external voltage terminal connected to another voltage terminal of first cell and second cell. The cell interface can prevent from occurring loop current in parallel cell.

Abstract: This invention relates is a Hall effect transformer, which include: Hall effect device, insulation layer and semiconductor, place the insulator layer between the Hall effect device and semiconductor used as an isolated, when AC current flow through the AC capacitors and Hall effect device, semiconductor corresponds to get both terminals of the AC voltage, and AC power transmission purposes.

Abstract: The invention related in cell parallel device is a circuit of SCR S1 to S4, comprises: a first terminal connected T1 to positive voltage terminal of first cell E1; a second terminal T2 connected to positive voltage terminal of second cell E2; and a third terminal T3 connected to voltage positive terminal of charge element CD or load LD, and trigger element TE connected between gate and anode of the SCR S1 to S4, the negative voltage terminal of charge element CD or load LD connected to negative voltage terminal of first cell E1 and second cell E2, can be not occur loop current in cells parallel circuit.

Abstract: The switch in this invention is connected in series with two field effect transistor, comprises: the source S1 of first N-channel FET F1 and the source S2 of second N-channel FET F2 are directly connected together form a third terminal VA, the gate G1 of first N-channel FET F1 and the gate G2 of second N-channel FET F2 are connected together form a control terminal GA, the drain D1 of first N-channel FET F1 form a first terminal D1, the drain D2 of second N-channel FET F2 form a second terminal D2, the body diode DA of first N-channel FET F1 and the body diode DB of second N-channel FET F2, are back-to-back series connected together, the right side equivalent circuit F are first N-channel FET F1 and second N-channel FET F2 equivalent circuit, form a switch F of the present invention.

Abstract: The invention related in cell interface is a circuit of diode D1 to D4, comprises: a first terminal connected to positive voltage terminal of first cell E1; a second terminal connected to positive voltage terminal of second cell E2; and a third terminal connected to external positive terminal VP, the external negative voltage terminal VN connected to negative voltage terminal of first cell E1 and second cell E2, can be not occur loop current in parallel circuit.

Abstract: An increase source to drain breakdown voltage vertical channel transistors device having a structure that is similar to that of a conventional metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate and a body. According the N+N? and P+P? junction theory of semiconductor, add to N? junction between the source N+ junction to P junction of N-Channel MOSFET; add to P? junction between the source P+ junction to n junction of P-Channel MOSFET; With the proposed MOSFET of which the source to drain breakdown voltage are increase may be achieved.

Abstract: A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off.

Abstract: This invention relates in Synchronous Rectifier Circuits, comprises: AC input terminal, switch, driving circuit, protect opposite current circuit and a load, to improved conventional Synchronous Rectifier Circuits, can be achieve rectify function.

Abstract: A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off.

Abstract: A rectifier driving circuit of the present invention, has a first driving element and a second driving element, switching element comprises a FET, a first driving element comprises the voltage drop resistor, a second driving element comprises the series-connected circuit of the diodes, the driving element for driving a FET, may be achieved rectify function.

Abstract: A single-ended forward converter of the present invention, has first and second switching element comprises a pair Lus N-Channel FET, a first driving circuit comprises the series-connected circuit of the first voltage drop resistor and first zener diode for driving first Lus N-Channel FET, a second driving circuit comprises the series-connected circuit of the second voltage drop resistor and second zener diode for driving second Lus N-Channel FET.

Abstract: A full-wave rectifier of the present invention, has an input AC power source, a pair of input terminal A and B, a pair of first and second switching element Q1 and Q2 comprises a first and a second Lus P-Channel FET, a pair of third and fourth switching element Q3 and Q4 comprises a third and a fourth Lus N-Channel FET, a pair of driving element R1 and R2, a load L1 and DC voltage output terminal C and D, the major function of AC to DC conversion.

Abstract: A power source apparatus is disclosed in this invention, specifically a power source apparatus comprising a voltage amplitude control unit that employs an active power factor corrector to control the output DC voltage by applying positive or negative logic control voltage, incorporated with high frequency power source circuit and high frequency transformer, brightness of Cold Cathode Fluorescent Lamp (CCFL) or External Electrode Fluorescent Lamp (EEFL) are controllable and DC power is directly applied to DC load. Such method is accomplished by adjusting the amplitude of the supplying DC voltage for controlling the amplitude of the high frequency voltage of CCFL or EEFL, thus called Voltage Amplitude Method. Because of the characteristics of stable frequency, high resolution and linearity, VAM is broadly used in the control of luminance of discharge tubes, such as TFT-LCD TVs, LCD monitors and advertisement lamps.

Abstract: A power MOSFET diode includes a plurality of unit elements, each of which has a gate and a drain that are connected to each other by the structure and the process of UMOS, VMOS, VDMOS, and etc., so as to integrate the unit elements into a PMD without any body diode of the traditional UMOS, VMOS, or VDMOS for providing a one-way electrical conductivity. The PMD is different from traditional diodes or Schottky diodes, because a forward bias is existed when the traditional diodes or Schottky diodes conduct the electricity on one-way. However, a drain-source on-state resistance (RDS) is used to replace the consumption of the forward bias when the PMD conducts the electricity on one-way. Due to the RDS of the PMD is lower and easy to be parallel connected to each other, the PMD can be used to substantially lower the power consumption and applied to various industries.

Abstract: The present controllable synchronous rectifier employs a Lus semiconductor to set synchronous rectification action in quadrant 1 of output characteristics of the conventional power MOSFETs. By controlling the voltage level of the gate-source voltage, the drain current can be controlled in the synchronous rectifier. Further, in combination with a protect opposite circuit to transfer a sinusoidal wave power supply or pulse power supply to a direct current power output, the synchronous rectifier is an indispensable high efficiency rectifier in the industry.