Patents by Inventor CHAO-CHIEH CHAN

CHAO-CHIEH CHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250047009
    Abstract: An antenna device and a forming method thereof are provided. The antenna device includes a substrate, a processing chip, a support, and an antenna assembly. The processing chip and the support are disposed on the two surfaces of the substrate. The antenna assembly is disposed on the surface of the support away from the substrate and electrically connected to the processing chip. The antenna assembly includes the first antenna structure and the second antenna structures. The first antenna structure is disposed on the support, and the normal direction thereof is parallel to the normal direction of the substrate. Each second antenna structure is disposed on one side of the first antenna structure and inclined relative to the substrate. The included angle between the normal direction of the second antenna structure and the normal direction of the substrate is greater than 0 degrees and less than 90 degrees.
    Type: Application
    Filed: June 26, 2024
    Publication date: February 6, 2025
    Inventors: Yi-Chih LEE, Chao-Chieh CHAN
  • Publication number: 20240055385
    Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.
    Type: Application
    Filed: May 11, 2023
    Publication date: February 15, 2024
    Inventors: KUO-HUA HSIEH, CHAO-CHIEH CHAN, MING-JHE WU, CHIH-YANG WENG
  • Publication number: 20240047323
    Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package, a first adhesive and a second adhesive. The substrate has a first board surface and a second board surface, and a second region surrounds a first region on the first board surface. The semiconductor package has an upper surface, a lower surface, and a side surface, and is disposed on the first board surface. The first adhesive is formed on the first board surface, in the second region and in a portion of the first region adjacent to the second region. The second adhesive is formed between the side surface and the first adhesive and contacts the side surface and the first adhesive, and the first adhesive and the second adhesive together form a pier adhesive.
    Type: Application
    Filed: March 14, 2023
    Publication date: February 8, 2024
    Inventors: KUO-HUA HSIEH, CHAO-CHIEH CHAN, YU-DA DONG, CHUN-JEN CHENG
  • Patent number: 11410901
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit board, a barrier structure and a molding layer. The circuit board includes a substrate and a component disposed on the substrate. The substrate includes a molding area and a non-molding area, and the component is disposed on the molding area. The barrier structure is disposed on the substrate and located between the molding area and the non-molding area. The barrier structure has a first predetermined height. The molding layer is disposed on the molding area and covers the component. The molding layer has a second predetermined height. The first predetermined height of the barrier structure is less than or equal to the second predetermined height of the molding layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: August 9, 2022
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Lee-Cheng Shen, Ying-Po Hung, Chao-Chieh Chan, Chao-Hsuan Wang
  • Publication number: 20210151358
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit board, a barrier structure and a molding layer. The circuit board includes a substrate and a component disposed on the substrate. The substrate includes a molding area and a non-molding area, and the component is disposed on the molding area. The barrier structure is disposed on the substrate and located between the molding area and the non-molding area. The barrier structure has a first predetermined height. The molding layer is disposed on the molding area and covers the component. The molding layer has a second predetermined height. The first predetermined height of the barrier structure is less than or equal to the second predetermined height of the molding layer.
    Type: Application
    Filed: August 26, 2020
    Publication date: May 20, 2021
    Inventors: LEE-CHENG SHEN, YING-PO HUNG, CHAO-CHIEH CHAN, CHAO-HSUAN WANG