Patents by Inventor Chao-Chih Hsiao
Chao-Chih Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180254004Abstract: A driving integrated circuit (IC) configured to drive a display panel and a fan-out compensation method thereof are provided. The driving IC includes a driving channel circuit and a compensation control circuit. The driving channel circuit outputs a pixel voltage in a normal operation period to drive a data line of the display panel. The driving channel circuit includes a compensation element configured to adjust an output resistance value, an output slew rate or an output timing of the output terminal of the driving channel circuit according to a setting value. The compensation control circuit is coupled to the data line of the display panel and the compensation element of the driving channel circuit, detects resistance information with respect to the data line in an initialization period, correspondingly adjusts the setting value according to the resistance information and outputs the setting value to the compensation element.Type: ApplicationFiled: March 6, 2017Publication date: September 6, 2018Applicant: Novatek Microelectronics Corp.Inventor: Chao-Chih Hsiao
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Patent number: 9524691Abstract: Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge unit, coupled to a gate line of the gate driving circuit for discharging the gate line to a first supply voltage; a first charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with a second supply voltage; a second charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with the second supply voltage; and a control circuit for controlling the first and the second charge units, and the discharge unit according to a timing controller of the LCD; wherein the control circuit sequentially turns on the first and the second charge units.Type: GrantFiled: May 29, 2015Date of Patent: December 20, 2016Assignee: NOVATEK Microelectronics Corp.Inventors: Po-Ching Li, Chao-Chih Hsiao
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Patent number: 9343029Abstract: A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage.Type: GrantFiled: July 1, 2010Date of Patent: May 17, 2016Assignee: NOVATEK Microelectronics Corp.Inventors: Ching-Ho Hung, Chao-Chih Hsiao, Yen-Po Chen, Bor-Chun Wu
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Publication number: 20150287377Abstract: Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge unit, coupled to a gate line of the gate driving circuit for discharging the gate line to a first supply voltage; a first charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with a second supply voltage; a second charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with the second supply voltage; and a control circuit for controlling the first and the second charge units, and the discharge unit according to a timing controller of the LCD; wherein the control circuit sequentially turns on the first and the second charge units.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Po-Ching Li, Chao-Chih Hsiao
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Patent number: 9078301Abstract: Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.Type: GrantFiled: March 7, 2012Date of Patent: July 7, 2015Assignee: NOVATEK Microelectronics Corp.Inventors: Po-Ching Li, Chao-Chih Hsiao
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Publication number: 20150161959Abstract: A driving method for a display system with a gate driving device and a panel includes utilizing a plurality of gate driving modules of the gate driving device to generate a plurality of gate driving signals for driving a plurality of scan lines of the panel; and adjusting a plurality of output resistances of the plurality of gate driving modules according to the plurality of gate driving signals.Type: ApplicationFiled: November 3, 2014Publication date: June 11, 2015Inventors: Chin-Hung Hsu, Yu-Ming Chang, Chao-Chih Hsiao, Po-Ching Li
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Publication number: 20130234626Abstract: Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Inventors: Po-Ching Li, Chao-Chih Hsiao
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Patent number: 8120603Abstract: A driver apparatus applied on a display is disclosed. The driver apparatus includes a voltage converter, an input level shift circuit, at least one input logic circuit, and at least one output level shifter. The voltage converter receives a first voltage, a ground voltage, and a second voltage, and generates an internal voltage according to the first voltage, the ground voltage, and the second voltage. The input level shift circuit receives an input signal, and generates a level shift input signal transiting between the first voltage and the second voltage according to the input signal. The input logic circuit receives the internal voltage, and generates an internal output signal transiting between the internal voltage and the second voltage according to the level shift input signal. The output level shifter generates a driving signal transiting between a third voltage and the second voltage according to the internal output signal.Type: GrantFiled: February 12, 2009Date of Patent: February 21, 2012Assignee: Novatek Microelectronics Corp.Inventor: Chao-Chih Hsiao
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Publication number: 20120007235Abstract: A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order.Type: ApplicationFiled: May 13, 2011Publication date: January 12, 2012Inventors: Chao-Chih Hsiao, Po-Ching Li
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Publication number: 20110102416Abstract: A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage.Type: ApplicationFiled: July 1, 2010Publication date: May 5, 2011Inventors: Ching-Ho Hung, Chao-Chih Hsiao, Yen-Po Chen, Bor-Chun Wu
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Patent number: 7894566Abstract: A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.Type: GrantFiled: July 17, 2009Date of Patent: February 22, 2011Assignee: Novatek Microelectronics Corp.Inventors: Chao-Chih Hsiao, Yen-Po Chen
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Publication number: 20100272228Abstract: A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.Type: ApplicationFiled: July 17, 2009Publication date: October 28, 2010Applicant: NOVATEK MICROELECTRONICS CORP.Inventors: Chao-Chih Hsiao, Yen-Po Chen
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Patent number: 7759979Abstract: A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.Type: GrantFiled: November 3, 2008Date of Patent: July 20, 2010Assignee: NOVATEK Microelectronics Corp.Inventors: Chao-Chih Hsiao, Yen-Po Chen
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Patent number: 7719306Abstract: In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.Type: GrantFiled: July 7, 2008Date of Patent: May 18, 2010Assignee: NOVATEK Microelectronics Corp.Inventor: Chao-Chih Hsiao
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Publication number: 20100103163Abstract: A driver apparatus applied on a display is disclosed. The driver apparatus includes a voltage converter, an input level shift circuit, at least one input logic circuit, and at least one output level shifter. The voltage converter receives a first voltage, a ground voltage, and a second voltage, and generates an internal voltage according to the first voltage, the ground voltage, and the second voltage. The input level shift circuit receives an input signal, and generates a level shift input signal transiting between the first voltage and the second voltage according to the input signal. The input logic circuit receives the internal voltage, and generates an internal output signal transiting between the internal voltage and the second voltage according to the level shift input signal. The output level shifter generates a driving signal transiting between a third voltage and the second voltage according to the internal output signal.Type: ApplicationFiled: February 12, 2009Publication date: April 29, 2010Applicant: NOVATEK MICROELECTRONICS CORP.Inventor: Chao-Chih Hsiao
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Publication number: 20100033225Abstract: A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.Type: ApplicationFiled: November 3, 2008Publication date: February 11, 2010Inventors: Chao-Chih Hsiao, Yen-Po Chen
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Publication number: 20090243656Abstract: In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.Type: ApplicationFiled: July 7, 2008Publication date: October 1, 2009Inventor: Chao-Chih Hsiao
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Patent number: 7292107Abstract: A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a modulator, a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N.Type: GrantFiled: October 17, 2005Date of Patent: November 6, 2007Assignee: Novatek Microelectronics Corp.Inventors: Chao-Chih Hsiao, Min-Chieh Hsu, Ping-Hsun Hsieh
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Publication number: 20060261906Abstract: A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N.Type: ApplicationFiled: October 17, 2005Publication date: November 23, 2006Inventors: Chao-Chih Hsiao, Min-Chieh Hsu, Ping-Hsun Hsieh