Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.

Abstract: A TV signal processing module includes a TV module, an internal transformer, and an external cable. The TV module is used for processing a TV signal. The internal transformer connected to the TV module is used for delivering the TV signal to the TV module. The internal transformer includes a high-voltage blocker for blocking a high-voltage signal to be applied to the TV module. The external cable, one end of which is connected to a TV cable and the other end of which is connected to the internal transformer, is used for sending the TV signal from the TV cable to the internal transformer.

Abstract: A noise-free bus circuit for diminishing noises of an original clock signal over a bus. The noise-free bus circuit has a connection wire module and a voltage detection circuit. The connection wire module includes the bus and a conduction wire disposed along the bus. The bus has a first end connected to the original clock signal while the conduction wire has a first end connected to a reference voltage. The voltage detection circuit is electrically connected to second ends of the bus and the conduction wire for generating an amended clock signal by determining a voltage difference between voltages at the second ends of the bus and of the conduction wire, the amended clock signal being equivalently equal to the original clock signal without the noises.

Abstract: OLE_LINK1A noise-free bus circuit for diminishing noises of an original clock signal over a bus. The noise-free bus circuit has a connection wire module and a voltage detection circuit. The connection wire module includes the bus and a conduction wire disposed along the bus. The bus has a first end connected to the original clock signal while the conduction wire has a first end connected to a reference voltage. The voltage detection circuit is electrically connected to second ends of the bus and the conduction wire for generating an amended clock signal by determining a voltage difference between voltages at the second ends of the bus and of the conduction wire, the amended clock signal being equivalently equal to the original clock signal without the noises.