Abstract: A liquid crystal display device of reducing power consumption includes a liquid crystal panel having a plurality of liquid crystal capacitors for displaying an image, an input interface for generating a scan control signal, an oscillator for generating a predetermined frequency, a control unit electrically coupled to the oscillator for outputting a current control signal when a frequency of the scan control signal is lower than the predetermined frequency, and a driving circuit electrically coupled to the controller for generating a first bias current to charge the plurality of liquid crystal capacitors of the liquid crystal panel.

Abstract: A source-driving circuit comprises a plurality of first and second data-outputting units, a first and a second charge-sharing units and a charge-sharing switch circuit. The first and second data-outputting units have corresponding first and second output terminals respectively for outputting data signals with a first polarity and a second polarity. The first and second charge-sharing units comprise a plurality of first and second switches respectively. Each first switch is electrically connected between each two first output terminals and each two second output terminals. Each second switch is electrically connected between one of the first outputting terminals and a corresponding one of the second outputting terminals. A charge-sharing switch circuit is electrically connected to the first and second charge-sharing units for outputting a switch signal to the first and second charge-sharing units according to a polarity signal, so as to determine the on/off statuses of the first and second switches.

Abstract: An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.

Abstract: The present invention provides a method for driving a liquid crystal display panel. The liquid crystal display panel has a plurality of pixels arranged in a matrix form and a plurality of data lines. The method includes generating gray level signals corresponding to the plurality of pixels according to input image data; determining whether the gray level values of the pixels in a same row corresponding to the plurality of data lines of a first color are all outside a first range; and when the gray level values of the pixels in the same row corresponding to the plurality of data lines of the first color are all outside the first range, controlling polarity of the gray level signals of the pixels in the same row corresponding to the plurality of data lines of the first color in a column inversion mode.

Abstract: A gate pulse modulating circuit includes a timing controller capable of generating an output enable signal and a plurality of timing control signals; a high gate voltage generating unit, electrically connected to the timing controller for receiving the timing control signals, capable of generating a high gate voltage with a waveform including a plurality of cutting edges in response to the timing control signals; a low gate voltage generating unit capable of generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal and the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, capable of generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges.

Abstract: An exemplary gate output control method includes the following steps: providing a gate control signal; using an angling control signal to angling modulate the gate control signal so as to generate a modulated gate control signal; and supplying the modulated gate control signal to a first integrated gate driver circuit and a second integrated gate driver circuit, to sequentially control the gate outputs of the first integrated gate driver circuit and the second integrated gate driver circuit. A duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the first integrated gate driver circuit is different from another duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the second integrated gate driver circuit.

Abstract: A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.

Abstract: A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.

Abstract: A liquid crystal display having adaptive driving mechanism includes plural pixel array areas and a driving module. Each pixel array area has a plurality of pixels. The driving module includes a signal generation unit for generating grey-level signals corresponding to the pixels based on input image data, a weighting conversion unit for converting the grey-level signals corresponding to the pixels into a plurality of weightings, a weighting processing unit for generating a weighting sum by summing up the weightings corresponding to the pixel array area, an inversion-mode setting unit for setting a polarity inversion mode according to the weighting sum, and a data signal output unit. The data signal output unit is utilized for providing a plurality of data signals to be written into the pixel array area based on the polarity inversion mode.

Abstract: A half source driving display panel includes a first to a fourth data line, a plurality of pixels, and a plurality of gate lines including a first and a second gate line. The two pixels disposed between the first and the second gate line and between the first and the second data line are driven by one of the first and the second gate line, and so do the two pixels disposed between the first and the second gate line and between the third and the fourth data line. Two pixels disposed between the first and the second gate line and between the second and the third data line are driven by the other one of the first and the second gate line.

Abstract: An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.

Abstract: A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

Abstract: The present invention provides a method for driving a liquid crystal display panel. The liquid crystal display panel has a plurality of pixels arranged in a matrix form and a plurality of data lines. The method includes generating gray level signals corresponding to the plurality of pixels according to input image data; determining whether the gray level values of the pixels in a same row corresponding to the plurality of data lines of a first color are all outside a first range; and when the gray level values of the pixels in the same row corresponding to the plurality of data lines of the first color are all outside the first range, controlling polarity of the gray level signals of the pixels in the same row corresponding to the plurality of data lines of the first color in a column inversion mode.

Abstract: A liquid crystal display includes a source driver, for generating a pixel data voltage, a gate driver, for generating a scanning signal voltage, and a plurality of pixel units. Each pixel unit includes a switch unit for delivering the pixel data voltage upon receiving the scanning signal voltage, a pixel electrode electrically coupled to the switch unit, a first electrode for supplying a first common voltage, a second electrode for supplying a second common voltage, a liquid crystal capacitor electrically coupled between the first electrode and the pixel electrode for driving liquid crystal layer in response to the pixel data voltage and the first common voltage, and a storage capacitor electrically coupled between the pixel electrode and the second electrode.

Abstract: An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.

Abstract: A source-driving circuit comprises a plurality of first and second data-outputting units, a first and a second charge-sharing units and a charge-sharing switch circuit. The first and second data-outputting units have corresponding first and second output terminals respectively for outputting data signals with a first polarity and a second polarity. The first and second charge-sharing units comprise a plurality of first and second switches respectively. Each first switch is electrically connected between each two first output terminals and each two second output terminals. Each second switch is electrically connected between one of the first outputting terminals and a corresponding one of the second outputting terminals. A charge-sharing switch circuit is electrically connected to the first and second charge-sharing units for outputting a switch signal to the first and second charge-sharing units according to a polarity signal, so as to determine the on/off statuses of the first and second switches.

Abstract: A level shifter includes at least one level shift unit for generating a corresponding clock-pulse output signal. The level shift unit receives a corresponding clock-pulse input signal. The clock-pulse output signal successively shares charges with respective auxiliary reference voltage sources to pull up a voltage level of the clock-pulse output signal from the second reference voltage to the first reference voltage. Alternatively, the clock-pulse output signal successively shares charges with respective auxiliary reference voltage sources to pull down the voltage level of the clock-pulse output signal from the first reference voltage to the second reference voltage.

Abstract: A gate pulse modulating circuit includes a timing controller capable of generating an output enable signal and a plurality of timing control signals; a high gate voltage generating unit, electrically connected to the timing controller for receiving the timing control signals, capable of generating a high gate voltage with a waveform including a plurality of cutting edges in response to the timing control signals; a low gate voltage generating unit capable of generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal and the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, capable of generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges.

Abstract: A polarity-reversible dimming controller having function of switching light source has a power supply module and a dimming control module. The dimming control module receives an external PWM dimming signal to control a feedback signal of the power supply module so as to dim or power on/off an LED lamp. The dimming control module has an output current switching circuit, a switch control circuit and a dimming control circuit. The output current switching circuit performs a PWM control over a current outputted from the power supply module by using the external PWM dimming signal to maintain chromacity of the LED lamp as a constant. The switch control circuit turns off the PWM controller to enter a standby mode for saving power once the PWM dimming signal exceeds a threshold value. As a full-wave rectification is performed on the PWM dimming signal, the polarity match issue upon assembling can be disregarded.

Abstract: A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.