Patents by Inventor Chao-Chiun Liang
Chao-Chiun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8791537Abstract: Disclosed is a flexible radiation detector including a substrate, a switching device on the substrate, an energy conversion layer on the switching device, a top electrode layer on the energy conversion layer, a first phosphor layer on the top electrode layer, and a second phosphor layer under the substrate.Type: GrantFiled: April 26, 2012Date of Patent: July 29, 2014Assignee: Industrial Technology Research InstituteInventors: Issac Wing-Tak Chan, Chao-Chiun Liang, Heng-Yin Chen, Ming-Hua Yeh
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Patent number: 8749723Abstract: A driving method for a panel structure including at least two liquid crystal layers is disclosed. The liquid crystal layers display different colors. When the panel structure includes a first liquid crystal layer and a second liquid crystal layer, the first and the second liquid crystal layers are initialized. A light source is utilized to emit the first and the second liquid crystal layers to write data to at least one of the first and the second liquid crystal layers. When the panel structure further includes a third liquid crystal layer, the first, the second and the third liquid crystal layers are first initialized. A light source is utilized to emit the first, the second and the third liquid crystal layers to write data to at least one of the first, the second and the third liquid crystal layers.Type: GrantFiled: January 29, 2010Date of Patent: June 10, 2014Assignee: Industrial Technology Research InstituteInventors: Shang-Chia Chen, Heng-Yin Chen, Chao-Chiun Liang
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Publication number: 20130161772Abstract: Disclosed is a flexible radiation detector including a substrate, a switching device on the substrate, an energy conversion layer on the switching device, a top electrode layer on the energy conversion layer, a first phosphor layer on the top electrode layer, and a second phosphor layer under the substrate.Type: ApplicationFiled: April 26, 2012Publication date: June 27, 2013Applicant: Industrial Technology Research InstituteInventors: Issac Wing-Tak Chan, Chao-Chiun Liang, Heng-Yin Chen, Ming-Hua Yeh
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Publication number: 20130107187Abstract: A pixel structure having a plurality of display regions is provided. The pixel structure includes a transparent substrate, an active device layer, and a plurality of reflective display units. The transparent substrate has a first side and a second side opposite to each other. The active device layer is disposed on one of the first side and the second side of the substrate. The reflective display units are respectively located in the display regions and driven by the active device layer. Two reflective display units are located at the same display region to provide different display colors. Two closely adjacent display regions provide different display colors when display simultaneously.Type: ApplicationFiled: April 17, 2012Publication date: May 2, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Min-Yao Lu, Yu-Yang Chang, Chao-Chiun Liang, Heng-Yin Chen
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Publication number: 20130100011Abstract: A human-machine interface device suitable for being electrically connected to an electronic device. The human-machine interface device includes a flexible carrier having at least one flexible portion, a bending sensor, and a control module. The bending sensor is disposed on the flexible portion of the flexible carrier. The control module is disposed on the carrier, connected to the bending sensor, and electrically connected to the electronic device. A first operation signal from the bending sensor is transmitted to the electronic device through the control module so that the electronic device performs according to the first operation signal.Type: ApplicationFiled: March 8, 2012Publication date: April 25, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Chung Lee, Chao-Chiun Liang, Ming-Hua Yeh, Chih-Jen Chen, Sheng-Po Wang
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Patent number: 8330882Abstract: An image display comprises at least one display device having a first pair of transparent conductive layers, a second pair of transparent conductive layers spaced apart from the first pair transparent conductive layers, a display layer disposed between the first pair of transparent conductive layers, the display layer configured to display an image in response to a first set of voltages applied to the first pair of transparent conductive layers, and a light control layer disposed between the second pair of transparent conductive layers, the light control layer configured to operate in one of a transmissive mode to allow an incident light to pass toward the display layer and a reflective mode to reflect an incident light away from the display layer in response to a second set of voltages applied to the second pair of transparent conductive layers.Type: GrantFiled: February 25, 2009Date of Patent: December 11, 2012Assignee: Industrial Technology Research InstituteInventors: Johnsee Lee, Chao-Chiun Liang, Tzeng-Shii Tsai
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Publication number: 20120194498Abstract: A bi-stable active matrix (AM) display apparatus and a method for driving a display panel thereof are provided. The bi-stable AM display apparatus includes a bi-stable AM display panel, a scan driver, a data driver and a controller. A frame period is divided into a resetting phase and a determining phase. The controller resets pixels on a plurality of scan lines of the bi-stable AM display panel to a homotropic state in the resetting phase through the scan driver and the data driver. The controller writes frame information into the pixels on the scan lines in the determining phase through the scan driver and the data driver.Type: ApplicationFiled: July 15, 2011Publication date: August 2, 2012Applicants: KENT STATE UNIVERSITY, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Deng-Ke Yang, Heng-Yin Chen, Young-Cheol Yang, Rafael S. Zola, Chao-Chiun Liang, Chih-Jen Chen
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Patent number: 8184131Abstract: A system for dynamic gamma correction of multi-scaled clocks and method therefor are provided, wherein multi-scaled clocks are applied to control the grayscale upon only one set of ramp voltage, so that the linearity of the gamma curve can be adjusted freely or to adjust the gamma correction strategy based on the image content or the user preference.Type: GrantFiled: February 20, 2007Date of Patent: May 22, 2012Assignee: Industrial Technology Research InstituteInventors: Chiao-Nan Huang, Chao-Chiun Liang
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Publication number: 20110037911Abstract: A driving method for a panel structure including at least two liquid crystal layers is disclosed. The liquid crystal layers display different colors. When the panel structure includes a first liquid crystal layer and a second liquid crystal layer, the first and the second liquid crystal layers are initialized. A light source is utilized to emit the first and the second liquid crystal layers to write data to at least one of the first and the second liquid crystal layers. When the panel structure further includes a third liquid crystal layer, the first, the second and the third liquid crystal layers are first initialized. A light source is utilized to emit the first, the second and the third liquid crystal layers to write data to at least one of the first, the second and the third liquid crystal layers.Type: ApplicationFiled: January 29, 2010Publication date: February 17, 2011Inventors: Shang-Chia CHEN, Heng-Yin Chen, Chao-Chiun Liang
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Publication number: 20100214501Abstract: An image display comprises at least one display device having a first pair of transparent conductive layers, a second pair of transparent conductive layers spaced apart from the first pair transparent conductive layers, a display layer disposed between the first pair of transparent conductive layers, the display layer configured to display an image in response to a first set of voltages applied to the first pair of transparent conductive layers, and a light control layer disposed between the second pair of transparent conductive layers, the light control layer configured to operate in one of a transmissive mode to allow an incident light to pass toward the display layer and a reflective mode to reflect an incident light away from the display layer in response to a second set of voltages applied to the second pair of transparent conductive layers.Type: ApplicationFiled: February 25, 2009Publication date: August 26, 2010Inventors: Johnsee Lee, Chao-Chiun Liang, Tzeng-Shii Tsai
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Publication number: 20100060624Abstract: A display unit including a capacitor, a pixel and a switch is provided. The capacitor is charged or discharged in response to a voltage difference between a drain control signal and a common voltage signal. The pixel displays in response to the voltage difference between the drain control signal and the common voltage signal. The switch is turned on according to a switch control signal and transmits a source control signal through the third terminal to the pixel and the capacitor. The switch is turned on twice within every one frame according to the switch control signal, and when the switch is turned on for the first time, the pixel displays, and when the switch is turned on for the second time, the capacitor is discharged to avoid a voltage at the third terminal of the switch to exceed a predetermined voltage.Type: ApplicationFiled: December 2, 2008Publication date: March 11, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Cheng Chen, Heng-Yin Chen, Chao-Chiun Liang
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Patent number: 7435355Abstract: A liquid-based gravity-driven etching-stop technique for controlling structure dimension is provided, where opposite etching trenches in cooperation with an etching-stop solution are used for controlling the dimension of a microstructure on the wafer level. In an embodiment, opposite trenches surrounding the microstructure are respectively etched on sides of the wafer, and the trench depth on the side of the wafer, on which the microstructure is, is equal to the design dimension of the microstructure. Contrarily, it is unnecessary to define the trench depth on the back-side of the chip. In the final step of the fabrication process, when the device is etched, such that the trenches on the sides communicate with each other to separate the microstructure from the whole wafer automatically and thereby shift from the etchant into the etching-stop solution to stop etching.Type: GrantFiled: October 5, 2005Date of Patent: October 14, 2008Assignee: Industrial Technology Research InstituteInventors: Wei-Chin Lin, Hui-Ling Chang, Ching-Hsiang Tsai, Chao-Chiun Liang, Gen-Wen Hsieh, Yuh-Wen Lee
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Publication number: 20080111836Abstract: A system for dynamic gamma correction of multi-scaled clocks and method therefor are provided, wherein multi-scaled clocks are applied to control the grayscale upon only one set of ramp voltage, so that the linearity of the gamma curve can be adjusted freely or to adjust the gamma correction strategy based on the image content or the user preference.Type: ApplicationFiled: February 20, 2007Publication date: May 15, 2008Inventors: Chiao-Nan Huang, Chao-Chiun Liang
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Patent number: 7208065Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.Type: GrantFiled: June 25, 2004Date of Patent: April 24, 2007Assignee: Industrial Technology Research InstituteInventors: Jing-Hung Chiou, Kai-Hsiang Yen, Chin-Horng Wang, Chao-Chiun Liang, Stella Y. H. Chen
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Publication number: 20060264058Abstract: A liquid-based gravity-driven etching-stop technique for controlling structure dimension is provided, where opposite etching trenches in cooperation with an etching-stop solution are used for controlling the dimension of a microstructure on the wafer level. In an embodiment, opposite trenches surrounding the microstructure are respectively etched on sides of the wafer, and the trench depth on the side of the wafer, on which the microstructure is, is equal to the design dimension of the microstructure. Contrarily, it is unnecessary to define the trench depth on the back-side of the chip. In the final step of the fabrication process, when the device is etched, such that the trenches on the sides communicate with each other to separate the microstructure from the whole wafer automatically and thereby shift from the etchant into the etching-stop solution to stop etching.Type: ApplicationFiled: October 5, 2005Publication date: November 23, 2006Inventors: Wei-Chin Lin, Hui-Ling Chang, Ching-Hsiang Tsai, Chao-Chiun Liang, Gen-Wen Hsieh, Yuh-Wen Lee
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Patent number: 6881369Abstract: The invention discloses a microelectroforming mold using a preformed metal as the substrate and its fabrication method. Using a preformed metal as the substrate can avoid deformation of the microelectroforming mold due to residual stress in the electroforming metal. The fabrication method disclosed herein includes the steps of: forming a layer of bonding material on a surface of the preformed metal substrate after machining; forming a high aspect ratio photoresist microstructure on surfaces of the metal substrate and the bonding material; putting an electroforming material into the gaps of the photoresist microstructure to form an electroforming metal microstructure; and using a thermal process to bond the metal substrate and the metal micro structure by the bonding material and simultaneously bum off the photoresist microstructure to form a micro-electroforming mold.Type: GrantFiled: April 18, 2002Date of Patent: April 19, 2005Assignee: Industrial Technology Research InstituteInventors: Yuh-Wen Lee, Liang-Yu Yao, Chao-Chiun Liang, Jeng-En Juang, Ching-Yi Wu
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Patent number: 6828164Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.Type: GrantFiled: April 1, 2003Date of Patent: December 7, 2004Assignee: Industrial Technology Research InstituteInventors: Jing-Hung Chiou, Kai-Hsiang Yen, Chin-Horng Wang, Chao-Chiun Liang, Stella Y. H. Chen
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Publication number: 20040231796Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.Type: ApplicationFiled: June 25, 2004Publication date: November 25, 2004Applicant: Industrial Technology Research InstituteInventors: Jing-Hung Chiou, Kai-Hsiang Yen, Chin-Horng Wang, Chao-Chiun Liang, Stella Y.H. Chen
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Publication number: 20040113148Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.Type: ApplicationFiled: April 1, 2003Publication date: June 17, 2004Inventors: Jing-Hung Chiou, Kai-Hsiang Yen, Chin-Horng Wang, Chao-Chiun Liang, Stella Y.H. Chen
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Patent number: 6734074Abstract: Within both a micro fabrication and a method for fabricating the micro fabrication there is formed over a substrate a spirally patterned conductor layer spirally topographically tapered in a vortex shape. The spirally patterned conductor layer is particularly useful as a microelectronic inductor structure within a microelectronic fabrication.Type: GrantFiled: January 24, 2002Date of Patent: May 11, 2004Assignee: Industrial Technology Research InstituteInventors: Wei-Su Chen, Hui-Chi Su, Yi-Shian Chen, Chao-Chiun Liang, Cheng Hong Lee, Jeng En Juang