Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor, and the transistor includes a gate structure with a bottom surface under the semiconductor surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer is extended beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure. The first conductive region includes a lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region. Wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide.

Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element. Wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: A DRAM structure includes a semiconductor substrate, a plurality of DRAM cells, a Bitline, a sense amplifier, and a local wordline. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The Bitline has a first terminal extended along the plurality of DRAM cells to a second terminal, and the Bitline is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the Bitline. The local wordline is connected to a gate terminal of the access transistor of a first DRAM cell in the plurality of DRAM cells. A refresh cycle time, a write cycle time, or a read cycle time of the DRAM structure is less than 5 ns.

Abstract: A semiconductor structure includes a semiconductor substrate, an epitaxy layer, a dielectric layer, a semiconductor layer, a first semiconductor device and a second semiconductor device. The semiconductor substrate has first region and a second region. The epitaxy layer is disposed on and within the first region of the semiconductor substrate. The dielectric layer is disposed on and within the second region of the semiconductor substrate. The semiconductor layer is disposed on the dielectric layer and within the second region. The first semiconductor device is formed on the epitaxy layer. The second semiconductor device is formed on the semiconductor layer.

Abstract: A composite semiconductor substrate includes a bulk semiconductor substrate and a first well region. The bulk semiconductor substrate has an original semiconductor surface and with a first doping type. The first well region is in the bulk semiconductor substrate with a second doping type, wherein the first doping type is different from the second doping type. There is no PN junction between the bulk semiconductor substrate and the first well region.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: The present invention provides a single monolithic die comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: A semiconductor device includes a substrate, a memory component and a heat dissipation component. The memory component is disposed on the substrate. The heat dissipation component is disposed on the substrate. The heat dissipation component has a thermal conductivity greater than that of silicon.

Abstract: A transistor structure includes a semiconductor body, a source region, a drain region and a gate region. The semiconductor body has a convex structure and the convex structure has at least four conductive channels extending upward. The source region contacts with a first end of the convex structure. The drain region contacts with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer is across over the convex structure. Two or four conductive channels are not parallel to each other, and there is no shallow trench isolation region among the at least four conductive channels.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor island, a shallow trench isolation (STI) region, a first buried layer, and a second buried layer. The semiconductor substrate has an original surface. The semiconductor island is formed based on the semiconductor substrate. The shallow trench isolation (STI) region surrounds the semiconductor island. The first buried layer is a localized layer under the semiconductor island, wherein a material of the first buried layer is different from that of the semiconductor substrate. The second buried layer is a localized layer under the first buried layer, wherein a material of the second buried layer is different from that of the semiconductor substrate.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.

Abstract: A semiconductor package includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling. The semiconductor package further includes an underground interconnection (UGI) disposed in a STI region of the processor die.

Abstract: A complementary metal-oxide-semiconductor (CMOS) circuit includes a bulk semiconductor substrate, a first active region and a second active region, a first type transistor, a first localized isolating layer, a second type transistor, and a second localized isolating layer. The bulk semiconductor substrate has an original semiconductor surface. The first active region and the second active region are formed based on the bulk semiconductor substrate. The first type transistor is formed based on the first active region and has a first doped body. The first localized isolating layer is under the first type transistor and at least isolates the first doped body from the bulk semiconductor substrate. The second type transistor is formed based on the second active region and has a second doped body. The second localized isolating layer is under the second type transistor and at least partially isolates the second doped body from the bulk semiconductor substrate.