Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has an original surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor and the transistor includes a gate structure with a bottom surface under the original surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer extends beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: The present application discloses a semiconductor package which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity (HTC) interconnects formed on, located between and/or placed side-by-side with the dies, a HTC substrate carrying all the dies, a HTC structural member, and a HTC heat spreader/heatsink with the dies and the HTC heat spreader thermally coupled to other HTC components in the semiconductor package. The semiconductor components can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual-or multi-sided cooling, power supply, and signaling.

Abstract: A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.

Abstract: A semiconductor package is provided, which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling.

Abstract: The present invention provides a fin structure transistor with precise and well-controlled geometries. Such fin structure transistor comprises a semiconductor substrate with an original surface and an active region formed based on the semiconductor substrate, the active region has a fin structure. A shallow trench isolation region surrounds the active region and a gate structure of the transistor crosses over the fin structure and covers a first portion of the shallow trench isolation region. Wherein the fin structure includes a fin body covered by the gate structure and a fin base portion of which is not covered by the gate structure, and a step-like transition is between the fin body and the fin base.

Abstract: An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.

Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

Abstract: A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.

Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.

Abstract: A method to process a diamond composite wafer includes the following steps: (a). forming a plurality of through vias in the diamond composite wafer and a first re-distribution layer on a firs side of the diamond composite wafer; (b). attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer; and (c). releasing the temporary carrier to form a circuit containing diamond composite wafer.

Abstract: A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

Abstract: A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

Abstract: A probe card system is provided. The probe card system, including a tester assembly, a probe head body configured to couple with the tester assembly, a first interconnection structure on a first side of the probe head body, and a probe layer structure on the first interconnection structure on the first side of the probe head body which is configured to engage with a wafer under test (WUT). The probe layer structure includes a sacrificial layer in connection with the first interconnection structure, a bonding layer in connection with the sacrificial layer, and a plurality of probe tips each in connection with respective conductive patterns exposed from the bonding layer and electrically coupled to the first interconnection structure. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing a probe card system is also provided.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: A semiconductor structure includes a bulk semiconductor substrate with an original semiconductor surface, a semiconductor island region, a shallow trench insulator (STI) region and a buried insulator layer. The semiconductor island region is formed based on the bulk semiconductor substrate. The STI region surrounds the semiconductor island region. The buried insulator layer is a localized insulator layer under the semiconductor island region, wherein a bottom surface of the semiconductor island region is fully isolated from the bulk semiconductor substrate by the buried insulator layer.