Patents by Inventor Chao-Chun Lu

Chao-Chun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253275
    Abstract: A semiconductor device includes a first semiconductor component and a second semiconductor component. The first semiconductor component includes a first substrate, a first dielectric layer and a first pad, wherein the first dielectric layer is disposed over the first substrate and has a first opening, and the first pad is disposed in the first opening. The second semiconductor component includes a second substrate, a second dielectric layer and a second pad, wherein the second dielectric layer is disposed over the second substrate and has a second opening, and the second pad is disposed in the second opening. The first dielectric layer is contact with the second dielectric layer, and the first pad is contact with the second pad.
    Type: Application
    Filed: February 6, 2025
    Publication date: August 7, 2025
    Applicants: nD-HI Technologies Lab, Inc., ETRON TECHNOLOGY, INC.
    Inventors: Ho-Ming TONG, Chao-Chun LU
  • Patent number: 12381123
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Grant
    Filed: December 27, 2024
    Date of Patent: August 5, 2025
    Assignee: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun Lu
  • Patent number: 12361998
    Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 15, 2025
    Assignees: Invention And Collaboration Laboratory Pte. Ltd., Etron Technology, Inc.
    Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
  • Publication number: 20250219042
    Abstract: An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.
    Type: Application
    Filed: February 25, 2025
    Publication date: July 3, 2025
    Inventors: HO-MING TONG, CHAO-CHUN LU
  • Patent number: 12341076
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Grant
    Filed: December 13, 2024
    Date of Patent: June 24, 2025
    Assignee: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun Lu
  • Patent number: 12341077
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Grant
    Filed: December 13, 2024
    Date of Patent: June 24, 2025
    Assignee: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun Lu
  • Publication number: 20250203838
    Abstract: A semiconductor cell structure includes a semiconductor substrate with an original semiconductor surface having a first set active regions and a second set of active regions; a STI region surrounding the first set and the second set active regions, a set of PMOS transistors disposed in the first set active regions; a set of NMOS transistors disposed in the second set of active regions; a VDD contacting line electrically coupled to the set of PMOS transistors; a VSS contacting line electrically coupled to the set of NMOS transistors; wherein a bottom surface of each of the source regions and drain regions of the PMOS transistors and the NMOS transistors is isolated from the semiconductor substrate by a localized insulator region, and these localized insulator regions are disposed below the original semiconductor surface.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 19, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventors: Chao-Chun LU, Juang-Ying CHUEH, Wen-Hsien TU
  • Publication number: 20250185280
    Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.
    Type: Application
    Filed: February 11, 2025
    Publication date: June 5, 2025
    Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun Lu
  • Publication number: 20250174539
    Abstract: A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 29, 2025
    Inventors: HO-MING TONG, CHIH-HSUN HSIEH, WEI YEN, CHAO-CHUN LU
  • Patent number: 12302554
    Abstract: An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: May 13, 2025
    Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun Lu
  • Publication number: 20250149375
    Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor, and the transistor includes a gate structure with a bottom surface under the semiconductor surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer is extended beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure. The first conductive region includes a lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure.
    Type: Application
    Filed: October 30, 2024
    Publication date: May 8, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventor: Chao-Chun Lu
  • Publication number: 20250140633
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 1, 2025
    Applicant: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun LU
  • Publication number: 20250125211
    Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region. Wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 17, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventor: Chao-Chun LU
  • Publication number: 20250125210
    Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element. Wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 17, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventor: Chao-Chun LU
  • Publication number: 20250118625
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 10, 2025
    Applicant: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun LU
  • Publication number: 20250112116
    Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: INVENTION AND COLLABORATION LABORATORY, INC.
    Inventor: Chao-Chun LU
  • Publication number: 20250104763
    Abstract: A DRAM structure includes a semiconductor substrate, a plurality of DRAM cells, a Bitline, a sense amplifier, and a local wordline. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The Bitline has a first terminal extended along the plurality of DRAM cells to a second terminal, and the Bitline is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the Bitline. The local wordline is connected to a gate terminal of the access transistor of a first DRAM cell in the plurality of DRAM cells. A refresh cycle time, a write cycle time, or a read cycle time of the DRAM structure is less than 5 ns.
    Type: Application
    Filed: September 20, 2024
    Publication date: March 27, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventors: Chao-Chun Lu, Chun Shiah, Shih-Hsing Wang
  • Publication number: 20250107242
    Abstract: A semiconductor structure includes a semiconductor substrate, an epitaxy layer, a dielectric layer, a semiconductor layer, a first semiconductor device and a second semiconductor device. The semiconductor substrate has first region and a second region. The epitaxy layer is disposed on and within the first region of the semiconductor substrate. The dielectric layer is disposed on and within the second region of the semiconductor substrate. The semiconductor layer is disposed on the dielectric layer and within the second region. The first semiconductor device is formed on the epitaxy layer. The second semiconductor device is formed on the semiconductor layer.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventors: Chao-Chun LU, Li-Ping HUANG
  • Publication number: 20250098297
    Abstract: A composite semiconductor substrate includes a bulk semiconductor substrate and a first well region. The bulk semiconductor substrate has an original semiconductor surface and with a first doping type. The first well region is in the bulk semiconductor substrate with a second doping type, wherein the first doping type is different from the second doping type. There is no PN junction between the bulk semiconductor substrate and the first well region.
    Type: Application
    Filed: September 13, 2024
    Publication date: March 20, 2025
    Applicant: Invention and Collaboration Laboratory, Inc.
    Inventor: Chao-Chun Lu
  • Patent number: 12255256
    Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: March 18, 2025
    Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun Lu