Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.

Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor includes a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.

Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die deposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrical connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.

Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

Abstract: Bond pad structures and semiconductor devices using the same. An exemplary semiconductor device comprises a substrate. An intermediate structure is formed over the substrate. A bond pad structure is formed over the intermediate structure. In one exemplary embodiment, the intermediate structure comprises a first metal layer neighboring and supporting the bond pad structure and a plurality of second metal layers underlying the intermediate structure, wherein one of the second metal layers functions as a power line.