Patents by Inventor Chao-Chun Tu
Chao-Chun Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105846Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Publication number: 20240107746Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Publication number: 20240098183Abstract: A marking method on image combined with sound signal, a terminal apparatus, and a server are provided. In the method, a first image is displayed. A selection command is detected. A target sound signal is embedded into a speech signal so as to generate a combined sound signal. The combined sound signal is transmitted. The selection command corresponds to a target region in the first image, and the selection command is generated selecting the target region through an input operation. The target sound signal corresponds to the target region of the selection command, and the speech signal is obtained by receiving sound. Accordingly, all attendants in the video conference are able to make makings on a shared screen.Type: ApplicationFiled: November 21, 2022Publication date: March 21, 2024Applicant: Acer IncorporatedInventors: Po-Jen Tu, Ming-Chun Fang, Jia-Ren Chang, Kai-Meng Tzeng, Chao-Kuang Yang
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Patent number: 8766417Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: GrantFiled: June 3, 2013Date of Patent: July 1, 2014Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Publication number: 20130264681Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Patent number: 8476745Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: GrantFiled: May 4, 2009Date of Patent: July 2, 2013Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Patent number: 7915744Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.Type: GrantFiled: November 18, 2009Date of Patent: March 29, 2011Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Yang-Hui Fang
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Publication number: 20100276805Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: ApplicationFiled: May 4, 2009Publication date: November 4, 2010Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Publication number: 20100065954Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.Type: ApplicationFiled: November 18, 2009Publication date: March 18, 2010Inventors: Chao-Chun Tu, Yang-Hui Fang
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Patent number: 7678659Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.Type: GrantFiled: June 2, 2006Date of Patent: March 16, 2010Assignee: MediaTek Inc.Inventors: Chao-Chun Tu, Ming-Chieh Lin
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Patent number: 7646087Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor includes a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.Type: GrantFiled: September 14, 2007Date of Patent: January 12, 2010Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Yang-Hui Fang
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Publication number: 20080001296Abstract: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die deposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrical connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.Type: ApplicationFiled: September 14, 2007Publication date: January 3, 2008Inventors: Chao-Chun Tu, Yang-Hui Fang
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Publication number: 20070072361Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.Type: ApplicationFiled: June 2, 2006Publication date: March 29, 2007Inventors: Chao-Chun Tu, Ming-Chieh Lin
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Publication number: 20060244156Abstract: Bond pad structures and semiconductor devices using the same. An exemplary semiconductor device comprises a substrate. An intermediate structure is formed over the substrate. A bond pad structure is formed over the intermediate structure. In one exemplary embodiment, the intermediate structure comprises a first metal layer neighboring and supporting the bond pad structure and a plurality of second metal layers underlying the intermediate structure, wherein one of the second metal layers functions as a power line.Type: ApplicationFiled: April 18, 2005Publication date: November 2, 2006Inventors: Tao Cheng, Chao-Chun Tu, Min-Chieh Lin, C.C. Mao, Hsiu Chen Peng, D. S. Chou