Abstract: A movement detection method, applied to a navigation input device with a navigation pattern comprising a center pattern and a radial pattern. The movement detection method comprises: (a)capturing a sensing image comprising a center pattern image and at least portion of a radial pattern image by an image sensor, wherein the center pattern image corresponds to the center pattern and the radial pattern image corresponding to the radial pattern; (b)computing a translation of the navigation input device according to shift of the center pattern image; and (c)computing a rotation angle of the navigation input device according to a first pattern relation between the center pattern image and a first portion of the radial pattern image. The translation and the rotation angle can be precisely and sensitively detected even if the joystick device is miniaturized, since the translation and the rotation angle are computed according to the navigation pattern.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.

Abstract: The present invention is a semiconductor device having a defect blocking region. The semiconductor device includes a substrate, a defect source region, a semiconductor layer and a defect blocking region. The defect source region is on the substrate, wherein the defect source region is a metamorphic buffer layer or a buffer layer, the semiconductor layer over the defect source region, wherein a lattice constant of the semiconductor layer is different from a lattice constant of the substrate. The defect blocking region is disposed on the substrate and below the semiconductor layer, wherein the defect blocking region includes a superlattice structure, wherein at least one of two adjacent layers of the superlattice structure has strain relative to the semiconductor layer, or a lattice constant of the superlattice structure is close to or equal to the lattice constant of the semiconductor layer.

Abstract: A heterojunction bipolar transistor structure is provided, including a substrate and a multi-layer structure formed on the substrate. The multi-layer structure includes a current clamping layer, and the current clamping layer can be disposed in a collector layer, disposed in a sub-collector layer, or interposed between a collector layer and a sub-collector layer. An electron affinity of the current clamping layer is less than an electron affinity of an epitaxial layer formed on the current clamping layer.

Abstract: A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

Abstract: A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A low input voltage boost converter operable at low temperatures, comprising a boost controller and an NMOS transistor. The boost controller has a driver unit, a first inverter circuit, a second inverter circuit, and a comparator circuit, wherein the first inverter circuit is used to enhance the high level of a switching signal during a startup period.