Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

Abstract: A measurement method for a vertical cavity surface emitting laser diode (VCSEL) and an epitaxial wafer test fixture are provided, especially the Fabry-Perot Etalon of the bottom-emitting VCSEL can be measured. When the Fabry-Perot Etalon of the bottom-emitting VCSEL is measured by a measurement apparatus, a light of the test light source of the measurement apparatus is incident from the substrate surface of the VCSEL epitaxial wafer such that the Fabry-Perot Etalon of the bottom-emitting VCSEL is acquired. Through the VCSEL epitaxial wafer test fixture, the bottom-emitting VCSEL can be directly measured by the existing measurement apparatus such that there is no need to change the optical design of the measurement apparatus, and it can prevent the VCSEL epitaxial wafer from being scratched or contaminated.

Abstract: Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.

Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Abstract: A joystick includes a casing, a stick body, an identification mark and an optical sensor. The casing has a hole. The stick body is movably disposed on the casing. The stick body has a first section and a second section. The first section penetrates through the hole to protrude from the casing, and the second section is inside the casing. The identification mark is disposed on the second section of the stick body. The identification includes a first line group and a second line group crossed to each other. The first line group and the second line group respectively has a plurality of lines with different widths and arranged adjacent to each other. The optical sensor is disposed inside the casing and adapted to acquire an identification image containing the identification mark to determine a gesture of the stick body.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A low input voltage boost converter operable at low temperatures, comprising a boost controller and an NMOS transistor. The boost controller has a driver unit, a first inverter circuit, a second inverter circuit, and a comparator circuit, wherein the first inverter circuit is used to enhance the high level of a switching signal during a startup period.