Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A vertical cavity surface emitting laser diode (VCSEL) includes a substrate, a lower Bragg reflector (DBR) layer, an active region, an upper Bragg reflector (DBR) layer, and a current confinement layer. The lower DBR layer is on the substrate. The active region is on the lower DBR layer on the active region. The current confinement layer is inside or outside the active region. When the current confinement layer comprises a compound containing phosphorus, such as AlAsP or AlGaAsP, and the phosphorus (P) content is within a specific range, the insulation rate of the current confinement layer will not be excessively fast to the point of being difficult to control. Additionally, the reproducibility of the aperture in the current confinement layer between batches of the VCSEL production is improved. Furthermore, the divergence angle of the VCSEL can be further reduced, thereby significantly enhancing the sensing capabilities of Lidar or 3D sensing.

Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

Abstract: A controller of a buck-boost conversion circuit and a mode switching method thereof are provided. The controller control operations of multiple switches of the buck-boost conversion circuit to convert an input voltage into an output voltage and provide an output current. The controller includes a slope compensation circuit, a control loop, and a mode switching circuit. The slope compensation circuit generates a slope compensation signal according to a mode switching signal of a current cycle. The control loop is coupled to the slope compensation circuit and the switches respectively, and is configured to generate multiple switch control signals according to the slope compensation signal, a feedback voltage related to the output voltage, and a current sense signal related to the output current to control the operations of the switches respectively. The mode switching circuit is coupled to the slope compensation circuit and the control loop.

Abstract: A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

Abstract: A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A low input voltage boost converter operable at low temperatures, comprising a boost controller and an NMOS transistor. The boost controller has a driver unit, a first inverter circuit, a second inverter circuit, and a comparator circuit, wherein the first inverter circuit is used to enhance the high level of a switching signal during a startup period.