Abstract: A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.

Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.

Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.

Abstract: Embodiments of the disclosure pertain to an optical transmitter and/or receiver comprising an electrical signal generator configured to generate an electrical signal that is unshielded or unshieldable at a predetermined frequency, a filter downstream from the electrical signal generator configured to reduce an amplitude of electromagnetic interference (EMI) at the predetermined frequency below a predetermined maximum value, an interface through which the EMI can pass in the absence of the filter, and an optical component configured to receive the electrical signal or provide an input signal to the electrical signal generator. A method of reducing EMI in an optical transmitter and/or receiver using the electrical signal generator, the filter and the optical component is also disclosed.

Abstract: Methods and apparatus for passivating a target are provided herein. For example, a method includes a) supplying an oxidizing gas into an inner volume of the process chamber; b) igniting the oxidizing gas to form a plasma and oxidize at least one of a target or target material deposited on a process kit disposed in the inner volume of the process chamber; and c) performing a cycle purge comprising: c1) providing air into the process chamber to react with the at least one of the target or target material deposited on the process kit; c2) maintaining a predetermined pressure for a predetermined time within the process chamber to generate a toxic by-product caused by the air reacting with the at least one of the target or target material deposited on the process kit; and c3) exhausting the process chamber to remove the toxic by-product.

Abstract: Embodiments of the disclosure pertain to an optical transmitter and/or receiver comprising an electrical signal generator configured to generate an electrical signal that is unshielded or unshieldable at a predetermined frequency, a filter downstream from the electrical signal generator configured to reduce an amplitude of electromagnetic interference (EMI) at the predetermined frequency below a predetermined maximum value, an interface through which the EMI can pass in the absence of the filter, and an optical component configured to receive the electrical signal or provide an input signal to the electrical signal generator. A method of reducing EMI in an optical transmitter and/or receiver using the electrical signal generator, the filter and the optical component is also disclosed.

Abstract: The present disclosure relates to a socket. The socket may include a housing and a plug. At least one of a slot or a hole may be positioned on at least one side of the housing. A clamping conducting strip may be positioned in the housing. At least two elastic conducting contacts may be positioned on a surface of plug. The elastic conducting contacts may connect to a power source and the plug may be positioned outside the housing. A connecting groove may be positioned on a back side of the housing. An inner contact point may be positioned in the connecting groove and be connected to the clamping conducting strip. A connector may be positioned in the plug. An external contact point may be positioned on the connector. The external contact point may be connected to the elastic conducting contact. The connector may be inserted into the connecting groove.

Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.

Abstract: A memory control system includes a memory interface, a microcontroller, and a sequence processing unit. The memory interface circuit receives a memory operation command and generates a plurality of operation instructions according to the memory operation command. The microcontroller is coupled to the memory interface circuit . The microcontroller receives the plurality of operation instructions and generates a plurality of task instructions according a scheduling algorithm through a predetermined protocol. The sequence processing unit is coupled to the microcontroller. The sequence processing unit receives the plurality of task instructions through the predetermined protocol, and controls a plurality of circuits of a memory device according to the plurality of task instructions with at least one finite state machine of the sequence processing unit.

Abstract: Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals.

Abstract: The present application relates to a socket. The socket may include a housing and a plug. At least one of a slot or a hole may be positioned on at least one side of the housing. A clamping conducting strip may be positioned in the housing. At least two elastic conducting contacts may be positioned on a surface of plug. The elastic conducting contacts may connect to a power source, and the plug may be positioned outside the housing. A connecting groove may be positioned on a back side of the housing. An inner contact point may be positioned in the connecting groove and be connected to the clamping conducting strip. A connector may be positioned in the plug. An external contact point may be positioned on the connector. The external contact point may be connected to the elastic conducting contact. The connector may be inserted into the connecting groove.

Abstract: A computing system includes a processing system with at least one processing unit. The processing system is configured to receive a depth map with a first boundary of an object. The processing system is configured to receive a color image that corresponds to the depth map. The color image includes a second boundary of the object. The processing system is configured to extract depth edge points of the first boundary from the depth map. The processing system is configured to identify target depth edge points on the depth map. The target depth edge points correspond to color edge points of the second boundary of the object in the color image. In addition, the processing system is configured to snap the depth edge points to the target depth edge points such that the depth map is enhanced with an object boundary for the object.

Abstract: Methods and apparatus for reducing arcing of a silicon oxide layer in a film stack are provided. In some embodiments a method for reducing arcing of a silicon oxide layer in a film stack includes: depositing a silicon oxide layer having a top surface atop a low-k dielectric layer, wherein the silicon oxide layer and low-k dielectric layer are disposed upon a substrate and within a film stack; contacting the silicon oxide layer with argon plasma in an amount sufficient to clean the silicon oxide layer; and depositing a nitride layer atop the silicon oxide layer.

Abstract: The present application relates to a socket. The socket may include a housing and a plug. At least one of a slot or a hole may be positioned on at least one side of the housing. A clamping conducting strip may be positioned in the housing. At least two elastic conducting contacts may be positioned on a surface of plug. The elastic conducting contacts may connect to a power source, and the plug may be positioned outside the housing. A connecting groove may be positioned on a back side of the housing. An inner contact point may be positioned in the connecting groove and be connected to the clamping conducting strip. A connector may be positioned in the plug. An external contact point may be positioned on the connector. The external contact point may be connected to the elastic conducting contact. The connector may be inserted into the connecting groove.

Abstract: Methods and apparatus for simulating arcing that can occur during substrate fabrication is provided. In some embodiments, the method includes: loading a bare silicon substrate that has been pretreated with at least one of polybutylene terephthalate (PBT) or a film into a testing environment, performing a physical vapor deposition (PVD) process on the bare silicon substrate, and determining arcing occurrences on the bare silicon substrate caused during the PVD process.

Abstract: Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals.

Abstract: Embodiments of a process chamber are provided herein. In some embodiments, a process chamber includes a chamber body having an interior volume, a substrate support disposed in the interior volume, a target disposed within the interior volume and opposing the substrate support, a process shield disposed in the interior volume and having an upper portion surrounding the target and a lower portion surrounding the substrate support, the upper portion having an inner diameter that is greater than an outer diameter of the target to define a gap between the process shield and the target, and a gas inlet to provide a gas to the interior volume through the gap or across a front opening of the gap to substantially prevent particles from the interior volume from entering the gap during use.

Abstract: Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals.

Abstract: Methods for depositing a dielectric oxide layer atop one or more substrates disposed in or processed through a PVD chamber are provided herein. In some embodiments, such a method includes: sputtering source material from a target assembly onto a first substrate while the source material is at a first erosion state and while providing a first amount of RF power to the target assembly to deposit a dielectric oxide layer onto a first substrate having a desired resistance-area; and subsequently sputtering source material from the target assembly onto a second substrate while the source material is at a second erosion state and while providing a second amount of RF power to the target assembly, wherein the second amount of RF power is lower than the first amount of RF power by a predetermined amount calculated to maintain the desired resistance-area.