Patents by Inventor Chao Fei
Chao Fei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12217732Abstract: An electronic device and a noise cancelation method thereof are provided. The electronic device includes a driver, a driven device, and an inertial measurement device. The driver is configured to generate a driving signal, and generate a noise prediction signal according to the driving signal. The driven device receives the driving signal to execute an operation, wherein the driven device generates a vibration noise according to generated vibrations when executing the operation. The inertial measurement device is configured to sense a position status of the electronic device to generate sensing information. The inertial measurement device receives the noise prediction signal, and compensates the sensing information according to the noise prediction signal to generate compensated sensing information.Type: GrantFiled: June 8, 2023Date of Patent: February 4, 2025Assignee: HTC CorporationInventors: Chao Shuan Huang, Jin-Rong Tsai, Chien Chou Chen, Po-Fei Chen
-
Patent number: 12125631Abstract: Shielded electrical transformers and power converters using those transformers are disclosed. In some implementations, a shielded electrical transformer includes a magnetic core, a primary winding, a first secondary winding, and a second secondary winding. The transformer includes a first shielding winding that has a same voltage potential direction as the primary winding and is connected in series with the primary winding to carry current that passes through the primary winding. The transformer also includes a second shielding winding that has a voltage potential direction opposite the primary winding and is connected from primary ground to a floating terminal. The first secondary winding, the second secondary winding, the first shielding winding, and the second shielding winding can each have an approximately equal number of turns.Type: GrantFiled: August 5, 2019Date of Patent: October 22, 2024Assignee: Google LLCInventors: Chao Fei, Honggang Sheng, Douglas Osterhout, Liang Jia, Srikanth Lakshmikanthan
-
Publication number: 20240308958Abstract: Disclosed is a method of preparing diroximel fumarate represented by the following structural formula (I) The method comprises reacting ethy lene carbonate with succinimide to form a hydroxyethyl succinimide intermediate; and reacting the intermediate with monomethyl fumarate to form the product compound.Type: ApplicationFiled: June 14, 2022Publication date: September 19, 2024Inventors: Daw-long Albert KWOK, Chao Fei, Erwin Irdam, Donald Walker, Markus Grohmann, Jens Mohr, Janina Bucher
-
Patent number: 11916478Abstract: In general, techniques are described that are directed to a device that includes a power storage device, an electrical load, and a first regulated power converter including components configured to generate, during a first time period and using electrical energy received from a power source external to the device, a first power signal to charge the power storage device. A second regulated power converter includes components configured to determine a charging current at which to charge the power storage device, determine a total amount of current flowing to the power storage device that includes current sourced by the second power converter less current sinked by the electrical load, and generate, during a second time period that is non-overlapping with the first time period, using electrical energy from the power source and based on determined the total amount of current, a second power signal to charge the power storage device.Type: GrantFiled: August 31, 2020Date of Patent: February 27, 2024Assignee: Google LLCInventors: Chao Fei, Douglas Osterhout, Srikanth Lakshmikanthan, Liang Jia, Li Wang
-
Publication number: 20230179010Abstract: In general, techniques are described that are directed to a device having a first power storage device and a second power storage device connected in series. A first power converter may generate, using electrical energy sourced from the first power storage device and the second power storage device, a first power signal to power a first set of components. A second power converter may generate, using electrical energy sourced from the first power storage device and not the second power storage device, a second power signal to power a second set of components.Type: ApplicationFiled: May 4, 2020Publication date: June 8, 2023Inventors: Chao Fei, Douglas Osterhout, Srikanth Lakshmikanthan
-
Publication number: 20220302734Abstract: In general, techniques are described that are directed to a device that includes a power storage device, an electrical load, and a first regulated power converter including components configured to generate, during a first time period and using electrical energy received from a power source external to the device, a first power signal to charge the power storage device. A second regulated power converter includes components configured to determine a charging current at which to charge the power storage device, determine a total amount of current flowing to the power storage device that includes current sourced by the second power converter less current sinked by the electrical load, and generate, during a second time period that is non-overlapping with the first time period, using electrical energy from the power source and based on determined the total amount of current, a second power signal to charge the power storage device.Type: ApplicationFiled: August 31, 2020Publication date: September 22, 2022Inventors: Chao Fei, Douglas Osterhout, Srikanth Lakshmikanthan, Liang Jia, Li Wang
-
Patent number: 11404967Abstract: Three-phase interleaved LLC and CLLC resonant converters, with integrated magnetics, are described. In various examples, the primary sides of the phases in the converters rely upon a half-bridge configuration and include resonant networks coupled to each other in delta-connected or common Y-node configurations. The secondary sides of the phases can rely upon a full-bridge configurations and are coupled in parallel. In one example, the transformers of the phases in the converters are integrated into one magnetic core. By changing the interleaving structure between the primary and secondary windings in the transformers, resonant inductors of the phases can also be integrated into the same magnetic core. A multi-layer PCB can be used as the windings for the integrated magnetics.Type: GrantFiled: June 12, 2018Date of Patent: August 2, 2022Assignee: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.Inventors: Chao Fei, Bin Li, Fred C. Lee, Qiang Li
-
Patent number: 11335648Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.Type: GrantFiled: November 27, 2019Date of Patent: May 17, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
-
Publication number: 20210366647Abstract: Shielded electrical transformers and power converters using those transformers are disclosed. In some implementations, a shielded electrical transformer includes a magnetic core, a primary winding, a first secondary winding, and a second secondary winding. The transformer includes a first shielding winding that has a same voltage potential direction as the primary winding and is connected in series with the primary winding to carry current that passes through the primary winding. The transformer also includes a second shielding winding that has a voltage potential direction opposite the primary winding and is connected from primary ground to a floating terminal. The first secondary winding, the second secondary winding, the first shielding winding, and the second shielding winding can each have an approximately equal number of turns.Type: ApplicationFiled: August 5, 2019Publication date: November 25, 2021Inventors: Chao Fei, Honggang Sheng, Douglas Osterhout, Liang Jia, Srikanth Lakshmikanthan
-
Patent number: 10950525Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: GrantFiled: September 3, 2019Date of Patent: March 16, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
-
Patent number: 10910140Abstract: A matrix transformer particularly suited to large voltage step-down, high current applications achieves increased good current sharing uniformity or air gap and electrical characteristics and reduced or eliminating termination losses, core losses and winding losses with a unitary magnetic core structure featuring sheets of magnetic material and a two-dimensional array of pillars on which windings, oriented in opposite directions on pillars that are adjacent in orthogonal directions, can be formed or placed comprising metallization on or embedded in a printed circuit board (PCB) structure. Magnetic flux density is reduced by at least one-half by dividing the magnetic flux in each pillar into two paths of increased width in the sheets of magnetic material. Magnetic flux density may be further decreased and flux uniformity improved by extending the sheets of magnetic material beyond a periphery defined by the pillar array.Type: GrantFiled: July 21, 2017Date of Patent: February 2, 2021Assignee: Virginia Tech Intellectual Properties, Inc.Inventors: Chao Fei, Fred C. Lee, Qiang Li
-
Publication number: 20200358314Abstract: A computing device can include a housing, a display secured by the housing, a charging coil included in a back side of the housing, the back side of the housing being on an opposite side from the display, and at least one magnet adjacent to the charging coil.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Vijayasekaran Boovaragavan, Veera Venkata Siva Nagesh Polu, Srikanth Lakshmikanthan, Douglas Osterhout, Liang Jia, Chao Fei, Zhenxue Xu
-
Patent number: 10790081Abstract: Three-phase interleaved LLC and CLLC resonant converters, with integrated magnetics, are described. In various examples, the primary sides of the phases in the converters rely upon a half-bridge configuration and include resonant networks coupled to each other in delta-connected or common Y-node configurations. The secondary sides of the phases can rely upon a full-bridge configurations and are coupled in parallel. In one example, the transformers of the phases in the converters are integrated into one magnetic core. By changing the interleaving structure between the primary and secondary windings in the transformers, resonant inductors of the phases can also be integrated into the same magnetic core. A multi-layer PCB can be used as the windings for the integrated magnetics.Type: GrantFiled: January 21, 2019Date of Patent: September 29, 2020Assignee: Virginia Tech Intellectual Properties, Inc.Inventors: Chao Fei, Bin Li, Fred C. Lee, Qiang Li, Hongfei Wu
-
Publication number: 20200220368Abstract: An adapter can include a voltage doubler rectifier, a first stage converter, and a second stage converter. The voltage doubler rectifier can have a switch and can be configured to rectify a received voltage in response to the switch being in a first position, and to rectify and effectively double the received voltage in response to the switch being in a second position. The first stage converter can be coupled to the voltage doubler rectifier and can be a first type of converter. The first type of converter can be either an isolated converter or a non-isolated converter. The second stage converter can be coupled to the first stage converter and can be a second type of converter. The second type of converter can be either the isolated converter or the non-isolated converter. The second type of converter can be different from the first type of converter.Type: ApplicationFiled: January 8, 2019Publication date: July 9, 2020Inventors: Chao Fei, Honggang Sheng, Douglas Osterhout, Srikanth Lakshmikanthan
-
Publication number: 20200098704Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
-
Patent number: 10522479Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.Type: GrantFiled: May 21, 2018Date of Patent: December 31, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
-
Publication number: 20190393134Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: ApplicationFiled: September 3, 2019Publication date: December 26, 2019Inventors: Li Zhong JIN, Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
-
Publication number: 20190379292Abstract: Three-phase interleaved LLC and CLLC resonant converters, with integrated magnetics, are described. In various examples, the primary sides of the phases in the converters rely upon a half-bridge configuration and include resonant networks coupled to each other in delta-connected or common Y-node configurations. The secondary sides of the phases can rely upon a full-bridge configurations and are coupled in parallel. In one example, the transformers of the phases in the converters are integrated into one magnetic core. By changing the interleaving structure between the primary and secondary windings in the transformers, resonant inductors of the phases can also be integrated into the same magnetic core. A multi-layer PCB can be used as the windings for the integrated magnetics.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: Chao Fei, Bin Li, Fred C. Lee, Qiang Li
-
Publication number: 20190355506Abstract: Three-phase interleaved LLC and CLLC resonant converters, with integrated magnetics, are described. In various examples, the primary sides of the phases in the converters rely upon a half-bridge configuration and include resonant networks coupled to each other in delta-connected or common Y-node configurations. The secondary sides of the phases can rely upon a full-bridge configurations and are coupled in parallel. In one example, the transformers of the phases in the converters are integrated into one magnetic core. By changing the interleaving structure between the primary and secondary windings in the transformers, resonant inductors of the phases can also be integrated into the same magnetic core. A multi-layer PCB can be used as the windings for the integrated magnetics.Type: ApplicationFiled: January 21, 2019Publication date: November 21, 2019Inventors: Chao Fei, Bin Li, Fred C. Lee, Qiang Li, Hongfei Wu
-
Patent number: 10446474Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: GrantFiled: December 21, 2017Date of Patent: October 15, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang