Abstract: Disclosed are a material pushing apparatus and a charging method thereof, and a material pushing machine and a material pushing method thereof. The material pushing apparatus comprises a charger (200) and a material pushing machine (100), and when the material pushing machine moves to the position where the charger is located, the charger can automatically supplement electric energy to the material pushing machine, such that the automation level of the material pushing apparatus is improved.

Abstract: A detection device includes a frame body and a main pipe positioning assembly, a branch pipe positioning assembly, and a first driving assembly disposed on the frame body. One side of the frame body is provided with an opening. The branch pipe positioning assembly is disposed inside the opening. The first driving assembly adjusts the branch pipe positioning assembly, so that the branch pipe positioning assembly is adapted to positions of the two branch pipes. During detection, the branch pipes are located in the opening, the main pipe positioning assembly connects two ends of the main pipe, and the branch pipe positioning assembly connects the two branch pipes. Two limiting members are slidably disposed on the frame body to open and close the opening, and the limiting members abut against an outer wall of the main pipe, such that the main pipe is located inside or outside the opening.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A driving substrate includes: a base substrate including first and second surfaces and side surfaces, at least one side surface being a selected side surface; a flexible film including a first region located on the first surface, a second region located on the second surface, and a bending region located between the first and second regions, the bending region including a first corner region, a second corner region and a side region; and a wiring layer, an electrode layer and a connection lead layer disposed in sequence on a side of the flexible film away from the base substrate. The wiring layer is located in the first region, the second region and the side region. The electrode layer includes first, second, third, and fourth electrodes. Each third electrode is electrically connected to a fourth electrode through the wiring layer. The connection lead layer includes first and second connection leads.

Abstract: A display panel includes a substrate, a light-blocking layer, a plurality of connection leads and a light-emitting device layer. The substrate includes a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface. At least one of the plurality of side surfaces is a selected side surface. The light-emitting device layer is disposed on the second surface. Each of the plurality of connection leads includes a first portion located on the first surface of the substrate, a second portion located on the selected side surface of the substrate and a third portion located on the second surface of the substrate. The light-blocking layer is located between the plurality of connection leads and the substrate, and is at least located between first portions of the plurality of connection leads and the first surface of the substrate.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: A display panel includes a first substrate, first electrodes, connection leads, a connection layer, a second substrate, and second electrodes disposed on a side of the second substrate away from the first substrate. The first substrate includes a first surface and a second surface that are opposite to each other and side surfaces connecting the first and second surfaces. At least one side surface is a selected side surface. The second substrate is disposed on the second surface. The connection layer bonds the first substrate and the second substrate. An orthographic projection of the connection layer on the second surface is located within an orthographic projection of the second substrate on the second surface. The connection leads extend from the first surface to the second surface through the selected side surface. Two ends of a connection lead are connected to a first electrode and a second electrode, respectively.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.

Abstract: A backlight module includes a light-emitting element, a quantum dot film, an optical film and a light adjusting element. The light-emitting element is adapted to emit a blue light. The quantum dot film is adapted to converting a first portion and a second portion of the blue light into a red light and a green light, respectively. The optical film is disposed on the quantum dot film. The light adjusting element is disposed between the optical film and the quantum dot film. The light adjusting element has a first surface and a second surface respectively facing the quantum dot film and the optical film. The first surface has multiple first optical microstructures. The first optical microstructures include multiple cones protruding toward the quantum dot film. Moreover, a display apparatus including the backlight module is also provided.

Abstract: A semiconductor structure includes channel structures vertically stacked, a gate structure engaging the channel structures, an epitaxial feature abutting the channel structures, a backside interconnect layer disposed under the epitaxial feature, and a backside metal contact disposed directly under the epitaxial feature and electrically coupling the epitaxial feature to the backside interconnect layer. In a cross-sectional view of the semiconductor structure along a lengthwise direction of the channel structures, the backside metal contact extends to a position directly under the channel structures.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: A package includes a first package structure and a second package structure stacked on and electrically connected to the first package structure. The first package structure includes an integrated circuit, conductive structures, and an encapsulant. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate. Sidewalls of the semiconductor substrate of the first chip are aligned with sidewalls of the semiconductor substrate of the fourth chip. The encapsulant laterally encapsulates the integrated circuit and the conductive structures. A topmost surface of the encapsulant is coplanar with top surfaces of the conductive structures. A bottommost surface of the encapsulant is coplanar with bottom surfaces of the conductive structures.

Abstract: A method, comprising: providing an adjustable distributor assembly disposed within a showerhead configured to provide selectively adjustable openings through which a cleaning material passes; determining an initial value of a configurable parameter of an adjustable distributor assembly; performing an amount/thickness measurement of a layer including polymeric residues and metal oxide deposits at a cleaning surface of a wafer by a monitoring device; determining whether a variation in the amount/thickness measurement is within an acceptable range; and in response to the variation in the amount/thickness measurement that is not within the acceptable range, automatically adjusting the configurable parameter of the adjustable distributor assembly to set the variation in the amount/thickness measurement within the acceptable range so that the cleaning material that passes through the selectively adjustable openings of the adjustable distributor assembly reduces metal oxide deposits.

Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.