Patents by Inventor Chao-Feng CAI
Chao-Feng CAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453956Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: GrantFiled: June 11, 2019Date of Patent: October 22, 2019Assignee: DELTA ELECTRONICS, INC.Inventors: Chao-Feng Cai, Jian-Hong Zeng, Zeng Li, Xiao-Ni Xin
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Publication number: 20190296150Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: Chao-Feng CAI, Jian-Hong ZENG, Zeng LI, Xiao-Ni XIN
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Patent number: 10347758Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: GrantFiled: July 12, 2017Date of Patent: July 9, 2019Assignee: DELTA ELECTRONICS, INC.Inventors: Chao-Feng Cai, Jian-Hong Zeng, Zeng Li
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Patent number: 9973185Abstract: A cascode switch device includes a cascode circuit, which includes a first switch and a second switch, and a protection circuit. The protection circuit is coupled between the first switch and the second switch. A first leakage current passing through the protection circuit is greater than or equal to a difference between a second leakage current and a third leakage current, and is smaller than an upper limit value of a leakage current of the cascode circuit. An upper limit value of a withstanding voltage is present between the first terminal and the control terminal of the first switch. When the first switch operates at the upper limit value of the withstanding voltage, the second leakage current is an upper limit value of a leakage current passing through the first switch, and the third leakage current is a lower limit value of a leakage current passing through the second switch.Type: GrantFiled: July 30, 2015Date of Patent: May 15, 2018Assignee: DELTA ELECTRONICS, INC.Inventors: Zeng Li, Chao-Feng Cai
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Patent number: 9917574Abstract: A switching circuit is disclosed. The switching circuit includes a normally-on switching element, a normally-off switching element, a switching unit and a power source. The drain of the normally-off switching element is electrically connected to the source of the normally-on switching element. The source of the normally-off switching element is electrically connected to the gate of the normally-on switching element. The power source and the switching unit are configured to form a serial-connected branch. A first terminal of the serial-connected branch is electrically connected to the drain of the normally-off switching element. A second terminal of the serial-connected branch is electrically connected to the source of the normally-off switching element.Type: GrantFiled: January 26, 2016Date of Patent: March 13, 2018Assignee: DELTA ELECTRONICS, INC.Inventor: Chao-Feng Cai
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Publication number: 20170309746Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Chao-Feng CAI, Jian-Hong ZENG, Zeng LI
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Patent number: 9755070Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: GrantFiled: March 23, 2016Date of Patent: September 5, 2017Assignee: DELTA ELECTRONICS, INC.Inventors: Chao-Feng Cai, Jian-Hong Zeng, Zeng Li
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Publication number: 20160344381Abstract: A switching circuit is disclosed. The switching circuit includes a normally-on switching element, a normally-off switching element, a switching unit and a power source. The drain of the normally-off switching element is electrically connected to the source of the normally-on switching element. The source of the normally-off switching element is electrically connected to the gate of the normally-on switching element. The power source and the switching unit are configured to form a serial-connected branch. A first terminal of the serial-connected branch is electrically connected to the drain of the normally-off switching element. A second terminal of the serial-connected branch is electrically connected to the source of the normally-off switching element.Type: ApplicationFiled: January 26, 2016Publication date: November 24, 2016Inventor: Chao-Feng Cai
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Publication number: 20160293755Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.Type: ApplicationFiled: March 23, 2016Publication date: October 6, 2016Inventors: Chao-Feng CAI, Jian-Hong ZENG, Zeng LI
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Publication number: 20160181788Abstract: A cascode switch device includes a cascode circuit, which includes a first switch and a second switch, and a protection circuit. The protection circuit is coupled between the first switch and the second switch. A first leakage current passing through the protection circuit is greater than or equal to a difference between a second leakage current and a third leakage current, and is smaller than an upper limit value of a leakage current of the cascode circuit. An upper limit value of a withstanding voltage is present between the first terminal and the control terminal of the first switch. When the first switch operates at the upper limit value of the withstanding voltage, the second leakage current is an upper limit value of a leakage current passing through the first switch, and the third leakage current is a lower limit value of a leakage current passing through the second switch.Type: ApplicationFiled: July 30, 2015Publication date: June 23, 2016Inventors: Zeng LI, Chao-Feng CAI