Patents by Inventor Chao Feng Yeh
Chao Feng Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916012Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
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Patent number: 10707314Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.Type: GrantFiled: September 29, 2017Date of Patent: July 7, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Seje Takaki, Jongsun Sel, Hisakazu Otoi, Chao Feng Yeh
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Patent number: 10355129Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.Type: GrantFiled: June 22, 2018Date of Patent: July 16, 2019Assignee: SanDisk Technologies LLCInventors: Chao Feng Yeh, TianChen Dong
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Patent number: 10290681Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.Type: GrantFiled: September 21, 2017Date of Patent: May 14, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Chao Feng Yeh, Jongsun Sel, Zhen Chen
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Publication number: 20190103467Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Seje TAKAKI, Jongsun SEL, Hisakazu OTOI, Chao Feng YEH
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Publication number: 20190088717Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Chao Feng YEH, Jongsun SEL, Zhen CHEN
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Patent number: 10115820Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.Type: GrantFiled: December 6, 2016Date of Patent: October 30, 2018Assignee: SanDisk Technologies LLCInventors: Chao Feng Yeh, TianChen Dong
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Publication number: 20180301556Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.Type: ApplicationFiled: June 22, 2018Publication date: October 18, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Chao Feng Yeh, TianChen Dong
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Patent number: 10079267Abstract: A gate dielectric layer and a gate electrode layer are formed around semiconductor pillars. The gate electrode layer is patterned to remove top portions that protrude above the semiconductor pillars and divided into multiple strips. Each strip constitutes a gate electrode line including a horizontal layer portion and a plurality of surrounding portions that entirely laterally surround respective channel regions of the semiconductor pillars to form wrap gate vertical select field effect transistors. Vertical stacks of memory elements and alternating layer stacks including a vertically alternating sequence of insulating strips and electrically conductive word line strips are formed above the vertical field effect transistors. Vertical bit lines can be formed inside the vertical stacks of memory elements.Type: GrantFiled: June 26, 2017Date of Patent: September 18, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Chao Feng Yeh, Tian Chen Dong
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Publication number: 20180158947Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.Type: ApplicationFiled: December 6, 2016Publication date: June 7, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Chao Feng Yeh, TianChen Dong
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Patent number: 8937011Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.Type: GrantFiled: January 15, 2013Date of Patent: January 20, 2015Assignee: SanDisk 3D LLCInventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh
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Patent number: 8802561Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.Type: GrantFiled: April 12, 2013Date of Patent: August 12, 2014Assignee: SanDisk 3D LLCInventors: Chao Feng Yeh, Hiroaki Iuchi, Hitomi Fujimoto, Hisayuki Nozawa
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Publication number: 20140170847Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.Type: ApplicationFiled: January 15, 2013Publication date: June 19, 2014Applicant: SANDISK 3D LLCInventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh