Patents by Inventor Chao Han CHENG
Chao Han CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735273Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.Type: GrantFiled: January 20, 2022Date of Patent: August 22, 2023Assignee: Western Digital Technologies, Inc.Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
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Publication number: 20220148659Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.Type: ApplicationFiled: January 20, 2022Publication date: May 12, 2022Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
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Patent number: 11264104Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.Type: GrantFiled: July 22, 2020Date of Patent: March 1, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
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Publication number: 20200350025Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
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Patent number: 10741256Abstract: A data storage system may include a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. Methods are also described.Type: GrantFiled: September 18, 2018Date of Patent: August 11, 2020Assignee: Western Digital Technologies, Inc.Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
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Patent number: 10613943Abstract: Systems, methods, and/or devices are used to manage open blocks within non-volatile storage devices, in order to improve the reliability of non-volatile storage devices. In some embodiments, when a shut-down request is received from a host device, the storage device fetches information about open blocks and their boundary regions susceptible to data reliability issues, and for each identified boundary region, the storage device programs a region contiguous to the identified boundary region. In some embodiments, the device updates an XOR parity table used for XOR parity management with the information that the region contiguous to the identified boundary is programmed. Subsequently, in some embodiments, the storage device can use the information, stored in the contiguous region and/or the XOR parity table, for data recovery in the event of a data loss. As a result, the reliability of the non-volatile storage device is improved.Type: GrantFiled: July 25, 2018Date of Patent: April 7, 2020Assignee: Western Digital Technologies, Inc.Inventors: Zelei Guo, Chao-Han Cheng, Nan Lu, Tienchien Kuo, Niles Nian Yang
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Publication number: 20200090760Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
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Patent number: 10482986Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.Type: GrantFiled: October 25, 2017Date of Patent: November 19, 2019Assignee: Western Digital Technologies, Inc.Inventors: Chao-Han Cheng, Nian Niles Yang, Anubhav Khandelwal, Chung-Yao Pai
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Patent number: 10452471Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.Type: GrantFiled: October 11, 2017Date of Patent: October 22, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Zhenlei Shen, Nian Niles Yang, Chao-Han Cheng
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Publication number: 20190122741Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Applicant: Western Digital Technologies, Inc.Inventors: Chao-Han Cheng, Nian Niles Yang, Anubhav Khandelwal, Chung-Yao Pai
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Publication number: 20190108090Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Zhenlei Shen, Nian Niles Yang, Chao-Han Cheng
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Publication number: 20190034290Abstract: Systems, methods, and/or devices are used to manage open blocks within non-volatile storage devices, in order to improve the reliability of non-volatile storage devices. In some embodiments, when a shut-down request is received from a host device, the storage device fetches information about open blocks and their boundary regions susceptible to data reliability issues, and for each identified boundary region, the storage device programs a region contiguous to the identified boundary region. In some embodiments, the device updates an XOR parity table used for XOR parity management with the information that the region contiguous to the identified boundary is programmed. Subsequently, in some embodiments, the storage device can use the information, stored in the contiguous region and/or the XOR parity table, for data recovery in the event of a data loss. As a result, the reliability of the non-volatile storage device is improved.Type: ApplicationFiled: July 25, 2018Publication date: January 31, 2019Inventors: Zelei Guo, Chao-Han Cheng, Nan Lu, Tienchien Kuo, Niles Nian Yang
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Patent number: 9537351Abstract: A dual input power supply system/method providing uninterruptable power to a protected load device (PLD) is disclosed. The system includes hybrid switch devices (HSD) comprising semiconductor and relay/contactors that minimize the OPERATE/RELEASE times associated with switchover from a primary power source (PPS) to a secondary power source (SPS). An operate/release controller (ORC) monitors the condition of power provided by the PPS and SPS and determines the optimal transfer time to activate the HSD and switch between the PPS and SPS based on the PLD configuration. Use of the HSD in conjunction with the ORC permits a wide variety of series permutated AC/DC primary (PPS) and secondary (SPS) power sources, EMI snubbers (EMS), bridge rectifier diodes (BRD), AC-DC converters (ADC), and DC-DC converters (DDC) to service the PLD, while simultaneously reducing storage capacitors normally required to cover the OPERATE/RELEASE times associated with traditional PPS/SPS switchover/failover delays.Type: GrantFiled: October 30, 2015Date of Patent: January 3, 2017Assignee: LITE-ON, INC.Inventors: Victor K. J. Lee, Yung Hsiang Liu, Wei Ru Chen, Chen Yu Wang, Chao Han Cheng
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Publication number: 20160233720Abstract: A dual input power supply system/method providing uninterruptable power to a protected load device (PLD) is disclosed. The system includes hybrid switch devices (HSD) comprising semiconductor and relay/contactors that minimize the OPERATE/RELEASE times associated with switchover from a primary power source (PPS) to a secondary power source (SPS). An operate/release controller (ORC) monitors the condition of power provided by the PPS and SPS and determines the optimal transfer time to activate the HSD and switch between the PPS and SPS based on the PLD configuration. Use of the HSD in conjunction with the ORC permits a wide variety of series permutated AC/DC primary (PPS) and secondary (SPS) power sources, EMI snubbers (EMS), bridge rectifier diodes (BRD), AC-DC converters (ADC), and DC-DC converters (DDC) to service the PLD, while simultaneously reducing storage capacitors normally required to cover the OPERATE/RELEASE times associated with traditional PPS/SPS switchover/failover delays.Type: ApplicationFiled: October 30, 2015Publication date: August 11, 2016Applicant: Lite-On, Inc.Inventors: Victor K. J. LEE, Yung Hsiang LIU, Wei Ru CHEN, Chen Yu WANG, Chao Han CHENG