Patents by Inventor Chao-Han Wu

Chao-Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747471
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: determining whether to use a first programming mode or a second programming mode to program memory cells according to a first data amount and a second data amount; when the first data amount is greater than the second data amount, programming the memory cells by using the first programming mode; and when the first data amount is not greater than the second data amount, programming the memory cells by using the second programming mode.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chao-Han Wu
  • Publication number: 20190332320
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: determining whether to use a first programming mode or a second programming mode to program memory cells according to a first data amount and a second data amount; when the first data amount is greater than the second data amount, programming the memory cells by using the first programming mode; and when the first data amount is not greater than the second data amount, programming the memory cells by using the second programming mode.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 31, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chao-Han Wu
  • Publication number: 20140129764
    Abstract: An allocation structure is used for a flash memory device. The flash memory device includes a first memory module and a second memory module. The first memory module and the second memory module respectively have a plurality of groups, and each of the groups of the first memory module has a plurality of physical blocks of the first memory module and each of the groups of the second memory module has a plurality of physical blocks of the second memory module. The allocation structure includes a first zone. The first zone is used to store a first allocation unit, and is formed by a first group of the groups of the first memory module and a first part of a second group of the groups of the second memory module.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 8, 2014
    Applicant: Solid State System Co., Ltd.
    Inventors: Chih-Hung Wang, Chao-Han Wu, Ting-Chung Hu
  • Patent number: 8713242
    Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 29, 2014
    Assignee: Solid State System Co., Ltd.
    Inventors: Chih-Hung Wang, Chao-Han Wu, Ting-Chung Hu
  • Publication number: 20140089566
    Abstract: A data storing method and a memory controller and a memory storage apparatus using the same are provided. The method includes logically grouping physical erase units into a data area and a spare area; selecting a physical erase unit form the spare area as a first data collecting unit; and selecting a physical erase unit from the spare area as a second data collecting unit. The method also includes writing data received from a host into the first data collecting unit. The method further includes performing a data arranging operation to move valid data in a third physical erase unit to the second data collecting unit and associating the third physical erase unit with the spare area. Accordingly, the method can effectively enhance the performance of the write operation.
    Type: Application
    Filed: November 7, 2012
    Publication date: March 27, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chao-Han Wu, Kim-Hon Wong, Kheng-Chong Tan
  • Publication number: 20120173791
    Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: SOLID STATE SYSTEM CO., LTD.
    Inventors: Chih-Hung Wang, Chao-Han Wu, Ting-Chung Hu