Patents by Inventor Chao-Hong Chen
Chao-Hong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937405Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.Type: GrantFiled: July 28, 2021Date of Patent: March 19, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chao-Jung Chen, Yu Nien Huang, Sin-Hong Lien, Jen-Mao Chen
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Publication number: 20240072411Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: Pegatron CorporationInventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
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Patent number: 11537893Abstract: A method and an electronic device for selecting deep neural network hyperparameters are provided. In an embodiment of the method, a plurality of testing hyperparameter configurations are sampled from a plurality of hyperparameter ranges of a plurality of hyperparameters. A target neural network model is trained by using a training dataset and the plurality of testing hyperparameter configurations, and a plurality of accuracies corresponding to the plurality of testing hyperparameter configurations are obtained after training for preset epochs. A hyperparameter recommendation operation is performed to predict a plurality of final accuracies of the plurality of testing hyperparameter configurations. A recommended hyperparameter configuration corresponding to the final accuracy having a highest predicted value is selected as a hyperparameter setting for continuing training the target neural network model.Type: GrantFiled: December 30, 2019Date of Patent: December 27, 2022Assignee: Industrial Technology Research InstituteInventors: Ming-Chun Hsyu, Chao-Hong Chen, Chien-Chih Huang
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Patent number: 11467081Abstract: A device and method for detecting particles by using electrical impedance measurement, in particular, relating to an improved electrical impedance measurement microfluidic chip and an improved particle detection method. The device comprises a sample injection part, a main channel (4) and an electrical impedance detection part. By means of said device and method, the present invention can accurately distinguish, detect and count different particles.Type: GrantFiled: August 30, 2018Date of Patent: October 11, 2022Assignee: NANJING YITIAN BIOTECHNOLOGY CO., LTD.Inventors: Chen-Yi Lee, Chao-Hong Chen, Chun-Kai Chiang, Yi Lu
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Publication number: 20220102274Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.Type: ApplicationFiled: June 10, 2021Publication date: March 31, 2022Inventors: Hung-Chung Chien, Chao-Hong Chen, Ming-Feng Shieh
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Publication number: 20210174210Abstract: A method and an electronic device for selecting deep neural network hyperparameters are provided. In an embodiment of the method, a plurality of testing hyperparameter configurations are sampled from a plurality of hyperparameter ranges of a plurality of hyperparameters. A target neural network model is trained by using a training dataset and the plurality of testing hyperparameter configurations, and a plurality of accuracies corresponding to the plurality of testing hyperparameter configurations are obtained after training for preset epochs. A hyperparameter recommendation operation is performed to predict a plurality of final accuracies of the plurality of testing hyperparameter configurations. A recommended hyperparameter configuration corresponding to the final accuracy having a highest predicted value is selected as a hyperparameter setting for continuing training the target neural network model.Type: ApplicationFiled: December 30, 2019Publication date: June 10, 2021Applicant: Industrial Technology Research InstituteInventors: Ming-Chun Hsyu, Chao-Hong Chen, Chien-Chih Huang
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Publication number: 20200209139Abstract: A device and method for detecting particles by using electrical impedance measurement, in particular, relating to an improved electrical impedance measurement microfluidic chip and an improved particle detection method. The device comprises a sample injection part, a main channel (4) and an electrical impedance detection part. By means of said device and method, the present invention can accurately distinguish, detect and count different particles.Type: ApplicationFiled: August 30, 2018Publication date: July 2, 2020Inventors: Chen-Yi Lee, Chao-Hong Chen, Chun-Kai Chiang, Yi Lu
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Publication number: 20200086320Abstract: A particulate matter detection device and a detection method, in particular, a detection device and detection method based on a dielectrophoresis and electrical impedance measurement technology is provided, and more in particular, an electrical impedance detection device utilizing a microfluidic chip, and an application thereof for detecting target particles are provided. The device comprises a sample introducing part, a main channel (3), a dielectrophoresis electric field generating part, and an electrical impedance measurement part. By using the dielectrophoresis electric field generating part to selectively control target cells, detection or counting is performed on a sample flexibly and precisely without the use of labels and antibodies.Type: ApplicationFiled: August 30, 2018Publication date: March 19, 2020Inventors: Chen-Yi Lee, Chao-Hong Chen, Jyun-Hong Wang, Yi Lu
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Patent number: 10324517Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.Type: GrantFiled: December 9, 2016Date of Patent: June 18, 2019Assignee: Industrial Technology Research InstituteInventors: Yung-Chieh Lin, Shih-Che Lin, Chao-Hong Chen, Liang-Chia Cheng
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Publication number: 20180120916Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.Type: ApplicationFiled: December 9, 2016Publication date: May 3, 2018Applicant: Industrial Technology Research InstituteInventors: Yung-Chieh Lin, Shih-Che Lin, Chao-Hong Chen, Liang-Chia Cheng