Abstract: Provided is a dual deposition chamber apparatus for producing silicon material, the apparatus including a furnace, a cooling jacket, a deposition device, and a vacuum extraction device. The cooling jacket communicates with the furnace, defines a space above the furnace, and includes an opening communicating with the space. The deposition device includes at least one first deposition substrate and at least one second deposition substrate. The at least one first deposition substrate and the at least one second deposition substrate are arranged side by side in the space, and respectively include a first inner wall surface and a second inner wall surface inclined downwards relative to a vertical axis. An uneven area is formed on the first inner wall surface and the second inner wall surface. The vacuum extraction device communicates with the opening of the cooling jacket.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: The present invention discloses an inverted organic photovoltaic cell comprising a polymerizable fullerene interlayer adapted to enhance the device performance and lifetime. The polymerizable fullerene derivative comprises a fullerene core, a bridging functional group and a polymerizable functional group. The fullerene core can be either C60 or C70, and the bridging functional group comprises a cyclic hydrocarbon or a heterocyclic ring. The polymerizable functional group comprises a thermally polymerizable functional group or a photochemically polymerizable functional group.

Abstract: The present invention discloses an inverted organic photovoltaic cell comprising a polymerizable fullerene interlayer adapted to enhance the device performance and lifetime. The polymerizable fullerene derivative comprises a fullerene core, a bridging functional group and a polymerizable functional group. The fullerene core can be either C60 or C70, and the bridging functional group comprises a cyclic hydrocarbon or a heterocyclic ring. The polymerizable functional group comprises a thermally polymerizable functional group or a photochemically polymerizable functional group.