Patents by Inventor Chao-Hsiang Li

Chao-Hsiang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11838828
    Abstract: An ultra-wideband assisted precise positioning system and an ultra-wideband assisted precise positioning method are provided. The method includes: arranging a plurality of device nodes in a target area; configuring a central control device node to communicatively connect to the device nodes; configuring the device nodes to perform a positioning process to obtain measured distances and positioning positions to be corrected; and configuring a central control processor to execute a positioning algorithm. The positioning algorithm includes: obtaining the measured distances and the positioning positions to be corrected; for each of the positioning positions to be corrected, performing a center-of-gravity weighting processing on neighboring points for obtaining initial guess positions; and obtaining the initial guess positions to input to an optimizer and optimize an objective function, and finding corrected positions with relatively smallest errors.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 5, 2023
    Assignee: PSJ INTERNATIONAL LTD.
    Inventors: Chao-Hsiang Li, Alexander I Chi Lai, Ruey-Beei Wu
  • Publication number: 20220386068
    Abstract: An ultra-wideband assisted precise positioning system and an ultra-wideband assisted precise positioning method are provided. The method includes: arranging a plurality of device nodes in a target area; configuring a central control device node to communicatively connect to the device nodes; configuring the device nodes to perform a positioning process to obtain measured distances and positioning positions to be corrected; and configuring a central control processor to execute a positioning algorithm. The positioning algorithm includes: obtaining the measured distances and the positioning positions to be corrected; for each of the positioning positions to be corrected, performing a center-of-gravity weighting processing on neighboring points for obtaining initial guess positions; and obtaining the initial guess positions to input to an optimizer and optimize an objective function, and finding corrected positions with relatively smallest errors.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 1, 2022
    Inventors: CHAO-HSIANG LI, ALEXANDER I CHI LAI, Ruey-Beei Wu
  • Publication number: 20100239711
    Abstract: A method is provided for manufacturing coffee by solid state fermentation, including the following steps: depositing coffee beans in a dust-free clean container; propagating a fungus with solid state fermentation; carrying out implantation process, wherein the fungus is implanted to the coffee beans contained in the dust-free clean container with a sterile operation, the fungus being one belonging to Eumycota, including at least one selected from Basidiomycotina and Ascomycotina; and performing a fermentation process. Also provided is a formula of the solid cultivation medium used in the method, which is suitable for both large-scale and small-scale production of fungi and is applicable to most fungi to not only increase the throughput as desired, but also provide a metabolic product containing pharmacologically active ingredients.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 23, 2010
    Inventors: Pei-Jung Li, Chao-Chia Li, Chao-Hsiang Li