Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A protection device for protecting an electronic device includes a current sensing module, for detecting a current flowing through a power supply path of the electronic device to generate a current signal; a processing device, coupled to the current sensing module, for receiving the current signal to determine whether the current corresponding to the current signal is greater than a first threshold value and outputting a control signal accordingly; a first switch, disposed on the power supply path, for controlling the power supply path to be switched on or off according to an input voltage of the power supply path; and a first control module, coupled to the processing device and the first switch, for controlling the first switch to be turned on or off according to the control signal outputted by the processing device, in order to control the power supply path to be switched on or off.

Abstract: A protection device for protecting an electronic device includes a current sensing module, for detecting a current flowing through a power supply path of the electronic device to generate a current signal; a processing device, coupled to the current sensing module, for receiving the current signal to determine whether the current corresponding to the current signal is greater than a first threshold value and outputting a control signal accordingly; a first switch, disposed on the power supply path, for controlling the power supply path to be switched on or off according to an input voltage of the power supply path; and a first control module, coupled to the processing device and the first switch, for controlling the first switch to be turned on or off according to the control signal outputted by the processing device, in order to control the power supply path to be switched on or off.

Abstract: A sole includes a base having a first gasbag and a second gasbag respectively received therein. The first gasbag and the second gasbag communicate with each other by multiple windpipes. Multiple through holes are respectively and laterally defined in two opposite walls of the base and respectively communicating with the first cavity and the second cavity. Each through hole has a check valve mounted therein. A first airtight cover is mounted to the first gasbag for closing the first gasbag and a second airtight cover is mounted to the second gasbag for closing the second gasbag. The first airtight cover has a blowing hole defined therein and communicates with the first gasbag. The second airtight cover has multiple blowing holes defined therein and communicating with the second gasbag. A ventilative insole connected to the first airtight cover.

Abstract: A sole includes a base having a first gasbag and a second gasbag respectively received therein. The first gasbag and the second gasbag communicate with each other by multiple windpipes. Multiple through holes are respectively and laterally defined in two opposite walls of the base and respectively communicating with the first cavity and the second cavity. Each through hole has a check valve mounted therein. A first airtight cover is mounted to the first gasbag for closing the first gasbag and a second airtight cover is mounted to the second gasbag for closing the second gasbag. The first airtight cover has a blowing hole defined therein and communicates with the first gasbag. The second airtight cover has multiple blowing holes defined therein and communicating with the second gasbag. A ventilative insole connected to the first airtight cover.

Abstract: A system of packing for turnkey services. An input port receives first and second wafer lots from a semiconductor manufacturer. The first wafer lot comprises a first number of dies, and the second wafer lot comprises a second number of dies. A packing device loads dies of the first wafer lot in a provided carrier having a preset capacity, and each of the loaded carriers is filled to capacity. A controller determines whether there is a remaining die of the first wafer lot that cannot fill one of the carriers, and directs the packing device to load the remaining dies of the first wafer lot and dies of the second wafer lot sequentially.

Abstract: In a foundry that produces a product family a system and method of reserving capacity for a pre-process order includes a plurality of products, a common pre-process operation and a plurality of distinct post-process operations corresponding to the products. When a pre-process order related to the pre-process operation from a customer is received, pre-process capacity and post-process operating capacity are reserved according to the pre-process order, and the pre-process capacity is provided for the pre-process. When a post-process order for a product corresponding to a specific post-process operation in the product family is received before a cutoff date, the reserved post-process operating capacity is provided for the corresponding post-process operation. If no post-process order is received before the cutoff date, the reserved post-process operating capacity is released as remnant supply. Other systems and methods are also provided.

Abstract: Within both a method for controlling microelectronic fabrication production and a system for controlling microelectronic fabrication production there is developed and evaluated for a plurality of microelectronic fabrication facilities a plurality of demand, allocation and output management plans prior to assigning and entering within at least one microelectronic fabrication facility a microelectronic fabrication order. The development and evaluation of the plurality of demand, allocation and output management plans provides for enhanced flexibility when assigning and entering the microelectronic fabrication order.

Abstract: Within both a method for controlling microelectronic fabrication production and a system for controlling microelectronic fabrication production there is developed and evaluated for a plurality of microelectronic fabrication facilities a plurality of demand, allocation and output management plans prior to assigning and entering within at least one microelectronic fabrication facility a microelectronic fabrication order. The development and evaluation of the plurality of demand, allocation and output management plans provides for enhanced flexibility when assigning and entering the microelectronic fabrication order.

Abstract: Within both a system for managing a work-in-process (WIP) workload within a fabrication facility and a method for managing the work-in-process (WIP) workload within the fabrication facility, there is determined from an overall routing sequence for fabricating the work-in-process (WIP) workload within the fabrication facility a series of routing sub-sequences which correspond with a series of service codes. By using the series of service codes for routing the work-in-process (WIP) workload within the fabrication facility there may be realized operational efficiencies when fabricating the work-in-process (WIP) workload within the fabrication facility.

Abstract: Within both a method for operating a fabrication facility and a system for operating the fabrication facility there is employed an auctioning of at least a portion of the total fabrication facility available capacity when operating the fabrication facility. By employing the auctioning of the at least the portion of the total fabrication facility available capacity the fabrication facility when operating the fabrication facility, the fabrication facility may be operated with enhanced fabrication facility utilization. The method and the system are particularly applicable to operating microelectronic fabrication facilities. Similarly, the method and the system preferably employ a distributed communications network, and in particular an Internet distributed communications network.

Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.

Abstract: A method for determining stress effects, or stress endurance of a film layer coated on a wafer during a scrubber clean process is disclosed. In the method, a wafer having a film layer coated on top is held in a stationary position while a high pressure water jet having a pressure larger than 60 kg/cm2 is scanned across a top surface of the film layer and through a center of the wafer. The total number of stress defects is then counted in the scanning path on top of the film layer as an indication of the stress endurance of the specific coating layer. The invention also discloses a method for scrubber cleaning a wafer surface which is coated with a film layer without causing stress defects in the film by rotating a silicon wafer, which has a film layer coated on top at a suitable rotational speed, and then scanning a water jet across a top surface of the film layer without passing through a center of the wafer. The water pressure utilized for the water jet may be suitably between 50 kg/cm2 and 75 kg/cm2.

Abstract: A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Abstract: A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.

Abstract: The present invention discloses a method for marking a wafer surface with minimized particulate contamination problem and further, the method is compatible with a chemical mechanical polishing method for planarization. An identification mark can be made on the non-patterned side of a wafer by a high energy laser beam either with or without an insulating layer deposited on top of the wafer. The method can also be carried out by first providing an identification mark on a non-patterned surface of the wafer and then, after all fabrication processes have been conducted on the patterned side of the wafer and a planarization process is conducted by a chemical mechanical polishing method, the identification mark on the backside of the wafer can be automatically read and then reproduced on the patterned side of the wafer prior to the shipment of the wafer to a customer or to a packaging facility.

Abstract: A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Abstract: The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.