Patents by Inventor Chao-Hsin Chi

Chao-Hsin Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7069456
    Abstract: A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventors: David S. Bormann, Chao-Hsin Chi, Frank P. Hart, Edwin J. Pole, II, Dong Tieu
  • Patent number: 7058836
    Abstract: A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: David S. Bormann, Chao-Hsin Chi, Frank P. Hart, Dong Tieu
  • Publication number: 20020087902
    Abstract: A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: David S. Bormann, Chao-Hsin Chi, Frank P. Hart, Dong Tieu
  • Publication number: 20020087898
    Abstract: A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: David S. Bormann, Chao-Hsin Chi, Frank P. Hart, Edwin J. Pole, Dong Tieu
  • Patent number: 5892931
    Abstract: The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal line, and two agents coupled to the bus and the third signal line. The first agent claims to be a target of a transaction on the bus without decoding the address associated with the transaction by asserting the first signal on the first signal line. The second agent responds to the transaction as the target. The second agent thereafter asserts a third signal on the third signal line to coordinate deassertion of the first signal on the first signal line by the first agent and concurrent assertion of the second signal on the second signal line by the second agent.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: April 6, 1999
    Assignee: Intel Corporation
    Inventors: Debra T. Cohen, Sung-Soo Cho, Chao-Hsin Chi, David Chang
  • Patent number: 5748918
    Abstract: A computer system has a first bus, a first bus bridge, and a second bus bridge. The first bridge connects the first bus to a second bus and the second bridge connects the first bus to a third bus. Normally, the first bridge behaves as the only subtractive decode agent on the first bus, claiming all transactions initiated on the first bus that target agents on the second bus or the third bus. If the first bridge claims a transaction targetting an agent on the third bus, the first bridge transfers the responsibility to respond to the transaction to the second bridge. The first bridge does not behave as the subtractive decode agent on the first bus when transactions are initiated on the second bus and forwarded to the first bus. In that case, the second bridge behaves as the subtractive decode agent on the first bus.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Sung-Soo Cho, Chao-Hsin Chi, David Chang