Patents by Inventor Chao-Hsin Chien
Chao-Hsin Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230327007Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Shu-Jui CHANG, Shin-Yuan WANG, Yu-Che HUANG, Chun-Liang LIN, Chao-Hsin CHIEN, Chenming HU
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Publication number: 20230253503Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien
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Patent number: 11670720Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.Type: GrantFiled: May 19, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien
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Publication number: 20230013047Abstract: An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.Type: ApplicationFiled: January 12, 2022Publication date: January 19, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Yu-Che CHOU, Li-Cheng TENG, Wan-Hsuan CHUNG, Chao-Hsin CHIEN
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Publication number: 20220165871Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.Type: ApplicationFiled: May 19, 2021Publication date: May 26, 2022Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien
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Publication number: 20210226059Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Chao-Hsin Chien, Yu-Che Chou, Chien-Wei Tsai, Chin-Ya Yi
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Patent number: 10971629Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.Type: GrantFiled: April 3, 2019Date of Patent: April 6, 2021Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung UniversityInventors: Chao-Hsin Chien, Yu-Che Chou, Chien-Wei Tsai, Chin-Ya Yi
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Publication number: 20200006566Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.Type: ApplicationFiled: April 3, 2019Publication date: January 2, 2020Inventors: Chao-Hsin Chien, Yu-Che Chou, Chien-Wei Tsai, Chin-Ya Yi
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Patent number: 10453688Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.Type: GrantFiled: August 31, 2016Date of Patent: October 22, 2019Assignees: National Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chung-Chun Hsu, Wei-Chun Chi
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Patent number: 10269966Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: GrantFiled: November 8, 2017Date of Patent: April 23, 2019Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
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Publication number: 20180069114Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
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Publication number: 20180061642Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chung-Chun HSU, Wei-Chun CHI
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Patent number: 9859276Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: GrantFiled: October 13, 2016Date of Patent: January 2, 2018Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Chiao-Tung UniversityInventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
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Patent number: 9837538Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: GrantFiled: July 20, 2016Date of Patent: December 5, 2017Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
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Publication number: 20170278962Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: ApplicationFiled: July 20, 2016Publication date: September 28, 2017Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
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Publication number: 20170125415Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: ApplicationFiled: October 13, 2016Publication date: May 4, 2017Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN
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Patent number: 9590105Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a first metal alloy over a first active region of a fin and a second metal alloy over a second active region of the fin. A conductive layer is over a channel region of the fin. A semiconductive layer is over the conductive layer. The conductive layer over the channel region suppresses current leakage and the semiconductive layer over the conductive layer reduces electro flux from a source to a drain, as compared to a channel region that does not have such a conductive layer or a semiconductive layer over a conductive layer. The semiconductor device having the first metal alloy as at least one of the source or drain requires a lower activation temperature than a semiconductor device that does not have a metal alloy as a source or a drain.Type: GrantFiled: April 7, 2014Date of Patent: March 7, 2017Assignees: National Chiao-Tung University, Taiwan Semiconductor Manufacturing Company LimitedInventors: Chao-Hsin Chien, Cheng-Ting Chung, Che-Wei Chen
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Patent number: 9502502Abstract: Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate.Type: GrantFiled: March 16, 2015Date of Patent: November 22, 2016Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung UniversityInventors: Samuel C. Pan, Chao-Hsin Chien, Chen-Han Chou
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Patent number: 9496259Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: GrantFiled: April 14, 2015Date of Patent: November 15, 2016Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO-TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
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Publication number: 20160307894Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: ApplicationFiled: April 14, 2015Publication date: October 20, 2016Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN