Abstract: An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.

Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

Abstract: A device includes a carbon nanotube having a channel region and dopant-free source/drain regions at opposite sides of the channel region, a first metal oxide layer interfacing a first one of the dopant-free source/drain regions of the carbon nanotube, a second metal oxide layer interfacing a second one of the dopant-free source/drain regions of the carbon nanotube and a gate structure over the channel region of the carbon nanotube, and laterally between the first metal oxide layer and the second metal oxide layer.

Abstract: A method includes following steps. A single-crystalline two-dimensional (2D) semiconductor layer is formed over a substrate. A single-crystalline 2D material layer is epitaxially grown on the single-crystalline 2D semiconductor layer. The single-crystalline 2D material layer is lattice-matched with the single-crystalline 2D semiconductor layer. A semiconductor device is over the single-crystalline 2D semiconductor layer.

Abstract: An epitaxial structure includes a substrate and a dielectric layer. The dielectric layer is on the substrate. The substrate comprises a single crystal metal or a single crystal 2D material. The dielectric layer is in physical contact with the substrate. The dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (FE) phase or antiferroelectric (AFE) phase.

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

Abstract: An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.

Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.