Abstract: A latch inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first level-adjusting unit and a second level-adjusting unit. The first level-adjusting unit changes the voltage level of the source of the second PMOS transistor in advance, and the second level-adjusting unit changes the voltage level of the drain of the second NMOS transistor in advance.

Abstract: An ESD (Electrostatic Discharge) circuit used in a multi-voltage system for protecting the system from electrostatic discharge between a first voltage source and at least one second voltage source. The ESD circuit includes a voltage bus, a first ESD protection circuit coupled between the first voltage source and the voltage bus, and a second ESD protection circuit coupled between the voltage bus and the second voltage source. The first ESD protection circuit includes an ESD detecting unit for detecting an electrostatic voltage and generating a trigger signal, and an ESD discharge unit for receiving the trigger signal of the ESD detecting unit and discharging an electrostatic current according to the trigger signal.

Abstract: A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

Abstract: A transmitter includes an output module coupled to an output port for outputting an output signal to the output port according to a detection signal, and a detect module for detecting the output port to generate the detect signal.

Abstract: An equalizer having an input end and an output end comprises: a first circuit, coupled between the input end and the output end, having a first gain; and a second circuit, coupled between the input end and the output end, having a second gain; wherein a frequency response of the equalizer corresponds to the first gain and the second gain.

Abstract: A voltage control oscillator includes a regulator and several voltage controlled delay cells. The regulator receives a control voltage and outputs an operation voltage. The voltage controlled delay cells are coupled to each other in serial to form a feedback circuit for outputting a clock signal. The delay cell includes a first inverter, a second inverter, and a cross latch. The first inverter receives a first input signal and outputs a first output signal, and the second inverter receives a second input signal and outputs a second output signal. The cross latch is used for latching the first output signal and the second output signal.

Abstract: A voltage control oscillator (VCO) whose gain coefficient is adjustable outputs a clock signal according to a control voltage. The VCO includes a replica bias unit, at least a delay cell, coupled to the replica bias unit, and a loading circuit. The replica bias unit outputs a first operational voltage according to the control voltage. The delay cell includes a voltage control delay line for outputting an output differential signal according to an input differential signal. The frequency of the output differential signal is adjusted by changing the impedance of the loading circuit.

Abstract: A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals.

Abstract: An adjustable resistor device is disclosed. The adjustable resistor device comprises a resistor and a plurality of metal oxide semiconductor (MOS) transistors coupled to the resistor. The MOS transistors are coupled in parallel and controlled by a plurality of corresponding control signals such that each of the MOS transistors is on either a triode region or a cutoff region.

Abstract: A low voltage differential signaling (LVDS) driving apparatus is disclosed, which comprises an LVDS output circuit to output an LVDS differential signal; a switch circuit coupled to the LVDS output circuit to control the phase of the LVDS differential signal; and a reference current control circuit to provide a control voltage to the LVDS output circuit such that the magnitude of the LVDS differential signal is determined based on the control voltage.

Abstract: A voltage control oscillating apparatus capable of automatically adjusting a oscillating frequency, comprising: a plurality of serial-coupled voltage control delay lines (VCDL) for outputting a plurality of oscillating signals respectively according to a voltage control signal, each of the oscillating signals is corresponding to a oscillating frequency; a multiplexer coupled to the VCDL for selecting one of the oscillating signals to be an output oscillating signal according to a control signal; a frequency detector coupled to the multiplexer for outputting a detecting signal according to the output oscillating signal; and a controller coupled to the frequency detector for outputting the control signal to the multiplexer according to the detecting signal.

Abstract: A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.