Patents by Inventor Chao-Hsuan Chuang

Chao-Hsuan Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6809616
    Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: October 26, 2004
    Assignee: Richtex Technology Corp.
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
  • Publication number: 20040201985
    Abstract: An automatic contrast compensation apparatus for an OLED display comprises a photo detector, an OLED driver, a safety clamping circuit, and a solar cell. When the intensity of environmental light increased, the photo detector sends a signal to the OLED driver to increase the brightness of the OLED display and for which, the solar cell provides the extra power for the OLED driver to improve the displaying performance of the OLED display in a power-saving manner. The safety clamping circuit prevents the OLED driver from over-current from the solar cell.
    Type: Application
    Filed: January 6, 2004
    Publication date: October 14, 2004
    Inventors: Nien-Hui Kung, Jing-Meng Liu, Der-Jiunn Wang, Chao-Hsuan Chuang
  • Patent number: 6747508
    Abstract: A resistance adjustable of resistance mirror circuit having a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value n I0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: June 8, 2004
    Assignee: Richtek Technology Corp.
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
  • Publication number: 20040085053
    Abstract: A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Inventors: Chao-Hsuan Chuang, Jing-Meng Liu, Cheng-Hsuan Fan, Kent Hwang
  • Publication number: 20040008096
    Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.
    Type: Application
    Filed: January 15, 2003
    Publication date: January 15, 2004
    Applicant: RichTek Technology Corp.
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
  • Publication number: 20030219004
    Abstract: In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.
    Type: Application
    Filed: May 24, 2002
    Publication date: November 27, 2003
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
  • Publication number: 20030141923
    Abstract: A resistance adjustable of resistance mirror circuit comprises: a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value nI0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.
    Type: Application
    Filed: August 28, 2002
    Publication date: July 31, 2003
    Applicant: Richtek Technology Corp.
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan