Patents by Inventor Chao-Hsuing Chen
Chao-Hsuing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10158004Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.Type: GrantFiled: July 17, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9853149Abstract: The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.Type: GrantFiled: October 3, 2016Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Fu-Jier Fan, Yi-Huan Chen, Kong-Beng Thei, Ker-Hsiao Huo, Szu-Hsien Liu
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Patent number: 9831314Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.Type: GrantFiled: August 3, 2015Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20170317186Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9735252Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.Type: GrantFiled: May 11, 2016Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9722082Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.Type: GrantFiled: April 21, 2016Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9691903Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.Type: GrantFiled: August 3, 2016Date of Patent: June 27, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsuing Chen, Hou-Yu Chen, Chie-Iuan Lin, Yuan-Shun Chao, Kuo Lung Li
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Publication number: 20170012128Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.Type: ApplicationFiled: August 3, 2016Publication date: January 12, 2017Inventors: Chao-Hsuing CHEN, Hou-Yu CHEN, Chie-Iuan LIN, Yuan-Shun CHAO, Kuo Lung LI
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Patent number: 9530889Abstract: A fin structure including a well layer, an oxide layer over the well layer and a channel layer over the oxide layer is formed. An isolation insulating layer is formed so that the channel layer protrudes from the isolation insulating layer and at least a part of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and over the isolation insulating layer. A recessed portion is formed by etching a part of the fin structure such that a surface of the well layer is exposed. An epitaxial layer is formed over the exposed well layer and over the channel layer. The epitaxial layer formed over the exposed well layer is modified such that etching selectivity of the modified layer against an alkaline solution with respect to a non-modified epitaxial layer is increased.Type: GrantFiled: May 21, 2015Date of Patent: December 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chao-Hsuing Chen
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Publication number: 20160343845Abstract: A fin structure including a well layer, an oxide layer over the well layer and a channel layer over the oxide layer is formed. An isolation insulating layer is formed so that the channel layer protrudes from the isolation insulating layer and at least a part of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and over the isolation insulating layer. A recessed portion is formed by etching a part of the fin structure such that a surface of the well layer is exposed. An epitaxial layer is formed over the exposed well layer and over the channel layer. The epitaxial layer formed over the exposed well layer is modified such that etching selectivity of the modified layer against an alkaline solution with respect to a non-modified epitaxial layer is increased.Type: ApplicationFiled: May 21, 2015Publication date: November 24, 2016Inventor: Chao-Hsuing CHEN
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Publication number: 20160254366Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9425313Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.Type: GrantFiled: July 7, 2015Date of Patent: August 23, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsuing Chen, Hou-Yu Chen, Chie-Iuan Lin, Yuan-Shun Chao, Kuo Lung Li
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Publication number: 20160240673Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9385215Abstract: Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate to produce a recess. An anisotropic etch stop layer is then formed by doping a bottom surface of the recess with a boron-containing dopant, which distorts the crystalline structure of the bottom surface. An anisotropic etch of the recess is then performed. The anisotropic etch stop layer resists anisotropic etching such that the recess comprises a substantially flat bottom surface after the anisotropic etch. The source or drain recess is then filled with a stress-inducing material to produce a strained channel.Type: GrantFiled: February 18, 2014Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9324836Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.Type: GrantFiled: August 13, 2015Date of Patent: April 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9269812Abstract: Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.Type: GrantFiled: January 20, 2015Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20150349090Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20150340447Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.Type: ApplicationFiled: August 3, 2015Publication date: November 26, 2015Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9196545Abstract: The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.Type: GrantFiled: June 16, 2014Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 9142642Abstract: A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.Type: GrantFiled: February 10, 2012Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin