Abstract: An ultraviolet (UV) sterilization system and monitoring method are applied to detect the working state of each UV lamp tube in an autonomous mobile robot. The monitoring method for UV sterilization includes enabling the autonomous mobile robot to move at a travel speed, driving the UV lamp to illuminate an UV, fetching an inductive voltage for each UV lamp, generating a report according to the inductive voltages for each UV lamp, and sending the report to a monitor server via the network from the autonomous mobile robot. Therefore, the monitoring server can check and record the working state of each UV lamp according to the report, and further the monitoring server will transmit a notification message to a client when the working state of any UV lamp is abnormal.

Abstract: A carrier tray and a carrier tray assembly using the same are described. The carrier tray includes a carrying portion, a surrounding wall and at least one recessed structure. The carrying portion has a top surface and a bottom surface opposite to the top surface. The surrounding wall is disposed around the carrying portion. The recessed structure is recessed into the carrying portion. The recessed structure has an opening and a recessed space, and the recessed space is communicated with the outside through the opening. There is a first distance defined by the recessed space along a first direction, and there is a second distance defined by the opening along the first direction. The first distance is greater than the second distance.

Abstract: Examples described herein relate to determining the waiting period using an agent. Examples include a source device transmitting a request to a target device to perform an action and waiting for a response to the request for an expected waiting period. Examples include an agent to detect an event at the target device and notify the source device to abort the request. The agent may determine an adjusted waiting period for completion of the action due to the event. For a new request, the source device may wait for a period corresponding to the adjusted waiting period.

Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure includes a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit can be folded or unfolded. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member positions the carried object on the carrying unit. A delivering device is provided for clamping and positioning a plurality of the packaging structures in an upright manner.

Abstract: A carrier tray and a carrier tray assembly using the same are described. The carrier tray includes a carrying portion, a surrounding wall and at least one recessed structure. The carrying portion has a top surface and a bottom surface opposite to the top surface. The surrounding wall is disposed around the carrying portion. The recessed structure is recessed into the carrying portion. The recessed structure has an opening and a recessed space, and the recessed space is communicated with the outside through the opening. There is a first distance defined by the recessed space along a first direction, and there is a second distance defined by the opening along the first direction. The first distance is greater than the second distance.

Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure comprises a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit is able to present as an unfolded state or a folded state. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member is used for positioning the carried object on the carrying unit. The invention also provides a delivering device for clamping and positioning a plurality of the aforementioned packaging structures in an upright manner.

Abstract: A method is provided for testing a semi-finished battery cell. The semi-finished battery cell is charged with a constant current when a voltage difference between the first conductor and the second conductor is less than a voltage threshold. The semi-finished battery cell is charged with a constant voltage when the voltage difference between the first conductor and the second conductor is equal to or larger than the voltage threshold. An overall electric quantity is obtained after a default time period, wherein the overall electric quantity is an electric quantity charged to the semi-finished battery cell with the constant current during the default time period. Accordingly, an insulation related to electrodes of the semi-finished battery cell is determined as poor when the overall electric quantity is larger than an electric quantity threshold.

Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

Abstract: A method is provided for testing a semi-finished battery cell. The semi-finished battery cell is charged with a constant current when a voltage difference between the first conductor and the second conductor is less than a voltage threshold. The semi-finished battery cell is charged with a constant voltage when the voltage difference between the first conductor and the second conductor is equal to or larger than the voltage threshold. An overall electric quantity is obtained after a default time period, wherein the overall electric quantity is an electric quantity charged to the semi-finished battery cell with the constant current during the default time period. Accordingly, an insulation related to electrodes of the semi-finished battery cell is determined as poor when the overall electric quantity is larger than an electric quantity threshold.

Abstract: The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.

Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.

Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: A probe includes a first electrical conductor, a second electrical conductor and a voltage measurer. The first electrical conductor has a first through hole, and the first through hole extends through two ends of the first electrical conductor. The second electrical conductor is detachably disposed on the first electrical conductor, and the second electrical conductor has a working surface and a second through hole. The working surface is located at an end of the second electrical conductor away from the first electrical conductor. Two ends of the second through hole that are opposite to each other are located at the working surface and an end of the first through hole, respectively. The first through hole is communicated with the second through hole. The voltage measurer is penetrating through the first through hole and the second through hole.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: A fin structure including a well layer, an oxide layer over the well layer and a channel layer over the oxide layer is formed. An isolation insulating layer is formed so that the channel layer protrudes from the isolation insulating layer and at least a part of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and over the isolation insulating layer. A recessed portion is formed by etching a part of the fin structure such that a surface of the well layer is exposed. An epitaxial layer is formed over the exposed well layer and over the channel layer. The epitaxial layer formed over the exposed well layer is modified such that etching selectivity of the modified layer against an alkaline solution with respect to a non-modified epitaxial layer is increased.

Abstract: A fin structure including a well layer, an oxide layer over the well layer and a channel layer over the oxide layer is formed. An isolation insulating layer is formed so that the channel layer protrudes from the isolation insulating layer and at least a part of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and over the isolation insulating layer. A recessed portion is formed by etching a part of the fin structure such that a surface of the well layer is exposed. An epitaxial layer is formed over the exposed well layer and over the channel layer. The epitaxial layer formed over the exposed well layer is modified such that etching selectivity of the modified layer against an alkaline solution with respect to a non-modified epitaxial layer is increased.

Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.