Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.

Abstract: An industrial device matching method and apparatus are used for acquiring a corresponding relationship between industrial devices in different industrial data sources to provide basis for industrial data analysis. The method, in an embodiment, includes collecting data of at least two industrial data sources; determining a first relationship between various industrial devices in each industrial data source, and determining a first relationship topology between the industrial devices in the industrial data source; and comparing the first relationship topologies corresponding to various industrial data sources, to determine a first corresponding relationship between industrial devices in industrial data sources, the first corresponding relationship enabling the first relationship topologies corresponding to at least two industrial data sources to be similar.

Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.

Abstract: A device implementing the subject high bit-depth graphics compression may include at least one processor configured to receive pixel data for a pixel block, obtain endpoints of a first bit length based on the pixel data in the pixel block, quantize the endpoints to a second bit length smaller than the first bit length, select the quantized endpoints for pixel values in the pixel block, determine a weight for each pixel of the pixel block in each of a plurality of planes corresponding to the endpoints selected for the pixel block, and generate a compressed data block representative of the pixel block based at least on the endpoints for the pixel block and the weight for each pixel of the pixel block in each of the plurality of planes corresponding to the endpoints. A method and computer program product implementing the subject high bit-depth graphics compression is also provided.

Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.

Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.

Abstract: An industrial device matching method and apparatus are used for acquiring a corresponding relationship between industrial devices in different industrial data sources to provide basis for industrial data analysis. The method, in an embodiment, includes collecting data of at least two industrial data sources; determining a first relationship between various industrial devices in each industrial data source, and determining a first relationship topology between the industrial devices in the industrial data source; and comparing the first relationship topologies corresponding to various industrial data sources, to determine a first corresponding relationship between industrial devices in industrial data sources, the first corresponding relationship enabling the first relationship topologies corresponding to at least two industrial data sources to be similar.

Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.

Abstract: A device implementing the subject high bit-depth graphics compression may include at least one processor configured to receive pixel data for a pixel block, obtain endpoints of a first bit length based on the pixel data in the pixel block, quantize the endpoints to a second bit length smaller than the first bit length, select the quantized endpoints for pixel values in the pixel block, determine a weight for each pixel of the pixel block in each of a plurality of planes corresponding to the endpoints selected for the pixel block, and generate a compressed data block representative of the pixel block based at least on the endpoints for the pixel block and the weight for each pixel of the pixel block in each of the plurality of planes corresponding to the endpoints. A method and computer program product implementing the subject high bit-depth graphics compression is also provided.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: The present invention discloses a light emitting device open/short detection circuit, which is used for detecting at least one light emitting device string open/short. Each light emitting device string has a first end and a second end, wherein the first end is coupled to a voltage supply circuit to supply electrical power to the light emitting devices. The open/short detection circuit includes: an abnormal voltage detection circuit coupled to the light emitting device strings for receiving voltages of the second ends respectively and generating an abnormal voltage detection signal; a voltage setting circuit coupled to the abnormal voltage detection circuit for setting an abnormal reference level; and a determination circuit coupled to the voltage setting circuit. When the abnormal voltage detection signal is equal to or over the abnormal reference level, the determination circuit generates an open/short detection signal for an abnormal condition detected.

Abstract: The present invention discloses a light emitting device open/short detection circuit, which is used for detecting at least one light emitting device string open/short. Each light emitting device string has a first end and a second end, wherein the first end is coupled to a voltage supply circuit to supply electrical power to the light emitting devices. The open/short detection circuit includes: an abnormal voltage detection circuit coupled to the light emitting device strings for receiving voltages of the second ends respectively and generating an abnormal voltage detection signal; a voltage setting circuit coupled to the abnormal voltage detection circuit for setting an abnormal reference level; and a determination circuit coupled to the voltage setting circuit. When the abnormal voltage detection signal is equal to or over the abnormal reference level, the determination circuit generates an open/short detection signal for an abnormal condition detected.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A cold cathode fluorescent lamp (CCFL) assembly includes a pair of CCFLs, and an inverter-type drive circuit. The drive circuit includes a first transformer having a primary winding adapted to be coupled to a power supply module, and a secondary winding with a pair of terminals. The CCFLs are coupled respectively to the terminals of the secondary winding. The drive circuit further includes a push-pull drive circuit coupled to the primary winding of the first transformer, and adapted to be coupled to the power supply module. The push-pull drive circuit excites the primary winding of the first transformer upon receiving power from the power supply module such that power is transferred from the primary winding to the secondary winding, thus activating the CCFLs coupled thereto.

Abstract: A cold cathode fluorescent lamp (CCFL) assembly includes a pair of CCFLs, and an inverter-type drive circuit. The drive circuit includes a first transformer having a primary winding adapted to be coupled to a power supply module, and a secondary winding with a pair of terminals. The CCFLs are coupled respectively to the terminals of the secondary winding. The drive circuit further includes a push-pull drive circuit coupled to the primary winding of the first transformer, and adapted to be coupled to the power supply module. The push-pull drive circuit excites the primary winding of the first transformer upon receiving power from the power supply module such that power is transferred from the primary winding to the secondary winding, thus activating the CCFLs coupled thereto.