Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including leads and a die paddle. A cavity is formed in the die paddle. Sidewall and bottom surfaces of the cavity are plated with a solder alloy material. A semiconductor die is attached to the bottom surface of the cavity by way of a thermal cycle. A molding compound encapsulates the semiconductor die, a portion of the leads, and a portion of the die paddle.

Abstract: Phase contrast microscopy images are collected of a liquid sample containing one or more microscopic objects. The images are analyzed to track the motion of the microscopic objects within the liquid sample. Using the updated locations of the tracking objects, a controller can generate control signals for controlling the microscopy parameters, to ensure that the portion of the liquid sample which is imaged includes the tracking objects. The tracking objects may be cells or cell-spheres. Thus, the system can, for example, track cells and cell-spheres, to observe their growth, during a long time-lapse experiment.

Abstract: A signal acquiring method of a GPS receiver and a digital camera thereof, suitable for accelerating a signal acquiring speed of the GPS receiver, are described. The signal acquiring method includes the following steps receiving a plurality of satellite signals; performing a discrete cosine transform (DCT) demodulation procedure, so as to parse a receiving time base of the satellite signals; next, transforming the satellite signals into a code information and a navigation frequency according to the receiving time base of the satellite signals; then, performing a correlation correction procedure to acquire a navigation information from the satellite signals according to the code information and the navigation frequency; which thus accelerates the processing speed on the signal acquiring flow through calculation characteristics of the DCT.

Abstract: A signal acquiring method of a GPS receiver and a digital camera thereof, suitable for accelerating a signal acquiring speed of the GPS receiver, are described. The signal acquiring method includes the following steps receiving a plurality of satellite signals; performing a discrete cosine transform (DCT) demodulation procedure, so as to parse a receiving time base of the satellite signals; next, transforming the satellite signals into a code information and a navigation frequency according to the receiving time base of the satellite signals; then, performing a correlation correction procedure to acquire a navigation information from the satellite signals according to the code information and the navigation frequency; which thus accelerates the processing speed on the signal acquiring flow through calculation characteristics of the DCT.

Abstract: A test key layout for finding open-via failures using an electron beam. Two types of test key layouts are designed. A first test key layout is used for finding open vias underneath even-numbered metallic layers while a second test key layout is used for finding open vias underneath odd-numbered metallic layers. A pair of neighboring metallic layers forms a group that has no direct electrical connection with other groups. The upper metallic layer in each group is in an open circuit state so that image contrast is enhanced.

Abstract: A method of detecting pattern bridge defects between two conductive layers in a test key area on a semiconductor wafer, further comprising a plurality of active areas, begins with forming a first conductive layer in the test key area. A dielectric layer is then formed in the test key area to cover the first conductive layer with a plug hole formed in the dielectric layer to a surface of the first conductive layer. A conductive plug is formed in the plug hole thereafter. A second conductive layer and a third conductive layer, a distance away from the second conductive layer, are formed atop the conductive plug in the test key area, and on other portions of thedielectric layer in the test key area, respectively. Simultaneously a fourth conductive layer and a fifth conductive layer, separated by a distance equal to the distance that separates the second conductive layer and the third conductive layer, are formed in each of the active layers.

Abstract: A test key layout for finding open-via failures using an electron beam. Two types of test key layouts are designed. A first test key layout is used for finding open vias underneath even-numbered metallic layers while a second test key layout is used for finding open vias underneath odd-numbered metallic layers. A pair of neighboring metallic layers forms a group that has no direct electrical connection with other groups. The upper metallic layer in each group is in an open circuit state so that image contrast is enhanced.