Patents by Inventor Chao-Hui Yeh

Chao-Hui Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522361
    Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 31, 2019
    Assignee: National Tsing Hua University
    Inventors: Zheng-Yong Liang, Chao-Hui Yeh, Jui-Hsiung Liu, Po-Wen Chiu
  • Publication number: 20190362979
    Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.
    Type: Application
    Filed: August 21, 2018
    Publication date: November 28, 2019
    Applicant: National Tsing Hua University
    Inventors: Zheng-Yong Liang, Chao-Hui Yeh, Jui-Hsiung Liu, Po-Wen Chiu
  • Patent number: 10466429
    Abstract: An optical fiber module contains: a circuit board, a photoelectric assembly, a control assembly, a body, and a light transmission set. The body includes a first accommodation groove, a second accommodation groove accommodating the optoelectronic assembly, a first reflection portion facing the circuit board, a lens set accommodated in the second accommodation groove and aligning with the first reflection portion, a guide orifice, a converging lens extending from the guide orifice, and a second reflection portion adjacent to the converging lens, wherein the second reflection portion has a second reflecting face corresponding to the converging lens. The light transmission set includes multiple passing faces formed on a first surface thereof so as to face and correspond to the first reflection portion of the body, and the light transmission set includes multiple complete reflecting faces formed on a second surface thereof away from the multiple passing faces individually.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 5, 2019
    Assignee: ORANGETEK CORPORATION
    Inventors: Guan-Fu Lu, Chun-Yi Yeh, Chun-Chieh Chen, Chao-Hui Kuo
  • Patent number: 10409013
    Abstract: An optical fiber module includes a main body and at least one optical conducting set. One surface of the main body is formed with a recess set and an accommodation groove, the main body is formed with a reflection slot and a lens slot, disposed with a lens set on a surface of the lens slot, and disposed with a third lens close to the accommodation groove; the optical conducting set is disposed in the accommodation groove and includes a base material and at least one optical conducting member, one surface of the base material is formed with an optical pervious plane close to the third lens which is substantially corresponding to the optical pervious plane, the optical conducting member are formed on two surfaces of the base materials, and can allow a light source with different wavelengths to pass and allow light sources with other wavelengths to be reflected.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 10, 2019
    Assignee: ORANGETEK CORPORATION
    Inventors: Guan-Fu Lu, Chun-Yi Yeh, Chun-Chieh Chen, Chao-Hui Kuo
  • Patent number: 10236181
    Abstract: A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 19, 2019
    Assignee: BEST CHAMPION TECHNOLOGY CO., LTD.
    Inventors: Chiu-Chuan Liao, Yi-Ping Lin, Chao-Hui Yeh
  • Publication number: 20190043720
    Abstract: A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventors: CHIU-CHUAN LIAO, YI-PING LIN, CHAO-HUI YEH
  • Publication number: 20170218536
    Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: CHAO-HUI YEH, JEN-KUAN CHIU
  • Patent number: 9691611
    Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 27, 2017
    Assignee: G-FORCE NANOTECH LTD.
    Inventors: Chao-Hui Yeh, Jen-Kuan Chiu
  • Publication number: 20170144888
    Abstract: A method for growing graphene by chemical vapor deposition is described. At least one substrate is loaded in a furnace. A reaction gas containing at least an oxygen-containing carbon source is introduced into the furnace. The reaction gas is heated and is UV-irradiated with a UV source, so that the carbon source is decomposed. A graphene film is deposited on a surface of the at least one substrate by the carbon atoms released by the decomposition of the carbon source.
    Type: Application
    Filed: March 17, 2016
    Publication date: May 25, 2017
    Inventors: Jen-Kuan Chiu, Chao-Hui Yeh, Po-Wen Chiu
  • Publication number: 20170090278
    Abstract: Provided is a pellicle film used for protecting an EUV lithographic mask including a first layer, a second layer, and a layered material. The second layer is formed on the first layer. The layered material is formed between the first layer and the second layer. The material of the layered material includes graphene, boron nitride, transition metal dichalcogenide, or a combination thereof.
    Type: Application
    Filed: March 29, 2016
    Publication date: March 30, 2017
    Inventors: Jen-Kuan Chiu, Chao-Hui Yeh
  • Publication number: 20170044667
    Abstract: A photo-assisted atomic layer deposition method includes the following steps: preparing a processing system having a processing chamber and a first gas input channel connecting the processing chamber, and the first gas input channel having a pre-chamber with a transparent side wall; introducing a first gas into the pre-chamber; illuminating the interior space of the pre-chamber by ultraviolet light via the transparent side wall; and injecting the first gas illuminated by the ultraviolet light into the processing chamber. The reactivity of the first gas can be promoted by the illumination of the ultraviolet light in the pre-chamber, so that the first gas illuminated by the ultraviolet light becomes more active to react completely in the process of film depositions, with reduced ligand residues in the deposited films.
    Type: Application
    Filed: April 8, 2016
    Publication date: February 16, 2017
    Applicant: G-FORCE NANOTECHNOLOGY LTD.
    Inventors: Chao-Hui Yeh, Jen-Kuan Chiu
  • Publication number: 20170025360
    Abstract: A semiconductor interconnect structure and a manufacturing method thereof are provided. The semiconductor interconnect structure includes a barrier metal layer, a copper metal layer, and a compound thin film. The barrier metal layer is formed on an interconnect trench, the copper metal layer is formed on the barrier metal layer, and the compound thin film is formed on a surface of the copper metal layer, wherein the compound thin film contains organocopper and amorphous carbon. Therefore, the resulting semiconductor interconnect structure has reduced resistivity.
    Type: Application
    Filed: September 10, 2015
    Publication date: January 26, 2017
    Inventors: Zheng-Yong Liang, Chao-Hui Yeh, Po-Wen Chiu
  • Publication number: 20160240376
    Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.
    Type: Application
    Filed: January 7, 2016
    Publication date: August 18, 2016
    Inventors: CHAO-HUI YEH, JEN-KUAN CHIU
  • Publication number: 20160233322
    Abstract: A method for fabricating a chalcogenide film is presented. The method includes providing a substrate in a chamber and performing a first atomic layer deposition process to form a first oxide film on the substrate; performing a first chalcogenization process including introducing a first chalcogen element to transform the first oxide film into a first chalcogenide film; and performing an annealing process on the first chalcogenide film.
    Type: Application
    Filed: December 30, 2015
    Publication date: August 11, 2016
    Inventors: CHAO-HUI YEH, JEN-KUAN CHIU
  • Publication number: 20140193574
    Abstract: The present invention discloses a graphene manufacturing system and the method thereof. In the prior arts, constant gas flows are used for the growth of graphene layers on work pieces. In contrast, the present invention makes use of multiple pulses of gas flows to grow graphene layers with low sheet resistivity.
    Type: Application
    Filed: July 3, 2013
    Publication date: July 10, 2014
    Inventor: Chao-Hui Yeh