Abstract: A two-dimensional semiconductor is configured for contacting two metals and includes a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer includes a channel region and two metal contacting regions. The two metal contacting regions are connected to two sides of the channel region, respectively. A plurality of heterojunctions having type-II band alignment are formed by the second semiconductor layers and the two metal contacting regions of the first semiconductor layer, respectively, and the heterojunctions are arranged and spaced away from each other.

Abstract: A semiconductor device includes a substrate, a bottom sublayer having a monoatomic layer thickness, disposed on the substrate, located at a bottom of the device, and extending in a horizontal direction, a metal sublayer having a monoatomic layer thickness, overlaying the bottom sublayer in the horizontal direction and electrically connected to the bottom sublayer, a top sublayer having a monoatomic layer thickness, disposed in the horizontal direction and electrically connected to the metal sublayer, and a contact metal layer disposed above the metal sublayer. A top surface of the contact metal layer is higher than a top surface of the top sublayer. Bottom layer contact metal atoms of the contact metal layer directly form corresponding bonds with a metal atom surface of the metal sublayer exposed after a portion of the top sublayer is stripped. Original corresponding bonds are maintained between the metal sublayer and the bottom sublayer.

Abstract: A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.

Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.

Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.

Abstract: A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.

Abstract: A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.

Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.

Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.

Abstract: A method for growing graphene by chemical vapor deposition is described. At least one substrate is loaded in a furnace. A reaction gas containing at least an oxygen-containing carbon source is introduced into the furnace. The reaction gas is heated and is UV-irradiated with a UV source, so that the carbon source is decomposed. A graphene film is deposited on a surface of the at least one substrate by the carbon atoms released by the decomposition of the carbon source.

Abstract: Provided is a pellicle film used for protecting an EUV lithographic mask including a first layer, a second layer, and a layered material. The second layer is formed on the first layer. The layered material is formed between the first layer and the second layer. The material of the layered material includes graphene, boron nitride, transition metal dichalcogenide, or a combination thereof.

Abstract: A photo-assisted atomic layer deposition method includes the following steps: preparing a processing system having a processing chamber and a first gas input channel connecting the processing chamber, and the first gas input channel having a pre-chamber with a transparent side wall; introducing a first gas into the pre-chamber; illuminating the interior space of the pre-chamber by ultraviolet light via the transparent side wall; and injecting the first gas illuminated by the ultraviolet light into the processing chamber. The reactivity of the first gas can be promoted by the illumination of the ultraviolet light in the pre-chamber, so that the first gas illuminated by the ultraviolet light becomes more active to react completely in the process of film depositions, with reduced ligand residues in the deposited films.

Abstract: A semiconductor interconnect structure and a manufacturing method thereof are provided. The semiconductor interconnect structure includes a barrier metal layer, a copper metal layer, and a compound thin film. The barrier metal layer is formed on an interconnect trench, the copper metal layer is formed on the barrier metal layer, and the compound thin film is formed on a surface of the copper metal layer, wherein the compound thin film contains organocopper and amorphous carbon. Therefore, the resulting semiconductor interconnect structure has reduced resistivity.

Abstract: A method and apparatus for fabricating two-dimensional layered chalcogenide film are provided. A catalyst gas, a metal-based precursor gas and a chalcogen-based precursor gas are ionized with external stimuli to generate energetic particles which facilitate a chalcogen-substitution reaction of a metal-based precursor gas in a reaction chamber to form uniform two-dimensional layered chalcogenide film of at least a single crystalline layer via chemical vapor deposition.

Abstract: A method for fabricating a chalcogenide film is presented. The method includes providing a substrate in a chamber and performing a first atomic layer deposition process to form a first oxide film on the substrate; performing a first chalcogenization process including introducing a first chalcogen element to transform the first oxide film into a first chalcogenide film; and performing an annealing process on the first chalcogenide film.

Abstract: The present invention discloses a graphene manufacturing system and the method thereof. In the prior arts, constant gas flows are used for the growth of graphene layers on work pieces. In contrast, the present invention makes use of multiple pulses of gas flows to grow graphene layers with low sheet resistivity.