Patents by Inventor Chao-Hung Wang
Chao-Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240143042Abstract: A computer case assembly is adapted for computer component units of a computer system to be mounted to. The computer component units include a motherboard and a power supply unit. The computer case assembly includes a main case module and a power case module. The main case module includes a main frame that is cuboid-shaped and that is adapted for the motherboard to be mounted to. The power case module includes a power case frame that is cuboid-shaped, that is adapted for the power supply unit to be mounted to, and that is detachably mounted to the main frame.Type: ApplicationFiled: December 29, 2022Publication date: May 2, 2024Inventors: Ling-Cheng TSAO, Chao-Hung WANG
-
Publication number: 20240136472Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
-
Publication number: 20240083981Abstract: The present invention relates to the treatment of herpes simplex virus (HSV) infection using an anti-HSV antibody. In particular, the anti-HSV antibody specifically binds to the glycoprotein D (gD) of herpes simplex virus-1 (HSV-1) and herpes simplex virus-2 (HSV-2). The treatment of the present invention is effective against drug-resistant and/or recurrent HSV infection.Type: ApplicationFiled: September 1, 2023Publication date: March 14, 2024Applicant: United BioPharma, Inc.Inventors: Be-Sheng KUO, Chao-Hung LI, Hsiao-Yun SHAO, Yaw-Jen LIU, Shugene LYNN, Chang Yi WANG
-
Publication number: 20240072411Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: Pegatron CorporationInventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
-
Patent number: 11886478Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.Type: GrantFiled: May 7, 2021Date of Patent: January 30, 2024Assignee: Yahoo Assets LLCInventors: Shaunak Mishra, Changwei Hu, Kevin Yen, Manisha Verma, Yifan Hu, Maxim Ivanovich Sviridenko, Avinash Chukka, Max Edward Beech, Chao-Hung Wang, Hua-Ying Tsai, Kamil Michal Zasadzinski, Wei Yu Lin, Yu Tian
-
Patent number: 11853890Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.Type: GrantFiled: July 26, 2019Date of Patent: December 26, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
-
Patent number: 11594266Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.Type: GrantFiled: March 9, 2021Date of Patent: February 28, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsuan Lin, Chao-Hung Wang
-
Publication number: 20220358153Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.Type: ApplicationFiled: May 7, 2021Publication date: November 10, 2022Inventors: Shaunak Mishra, Changwei Hu, Kevin Yen, Manisha Verma, Yifan Hu, Maxim Ivanovich Sviridenko, Avinash Chukka, Max Edward Beech, Chao-Hung Wang, Hua-Ying Tsai, Kamil Michal Zasadzinski, Wei Yu Lin, Yu Tian
-
Patent number: 11138497Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.Type: GrantFiled: December 18, 2018Date of Patent: October 5, 2021Assignee: MACRONIX INTERNATIONAL CO., LTDInventors: Yu-Hsuan Lin, Chao-Hung Wang, Ming-Hsiu Lee
-
Publication number: 20210193201Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Inventors: Yu-Hsuan LIN, Chao-Hung WANG
-
Patent number: 10970044Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.Type: GrantFiled: May 9, 2019Date of Patent: April 6, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Hsiu Lee, Chao-Hung Wang
-
Patent number: 10971200Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.Type: GrantFiled: October 9, 2018Date of Patent: April 6, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsuan Lin, Chao-Hung Wang
-
Publication number: 20200349428Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.Type: ApplicationFiled: July 26, 2019Publication date: November 5, 2020Inventors: Chao-Hung WANG, Yu-Hsuan LIN, Ming-Liang WEI, Dai-Ying LEE
-
Publication number: 20200227414Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105? to 109?, and the second resistance is larger than the first resistance.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Chao-Hung WANG, Yu-Hsuan LIN, Dai-Ying LEE
-
Patent number: 10713410Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.Type: GrantFiled: April 25, 2019Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
-
Publication number: 20200133635Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.Type: ApplicationFiled: May 9, 2019Publication date: April 30, 2020Inventors: Ming-Hsiu LEE, Chao-Hung WANG
-
Publication number: 20200058859Abstract: A resistive memory device includes a first electrode, a resistance switching layer and a second electrode. The resistance switching layer is disposed on the first electrode and includes a ternary transition metal oxide. The second electrode is disposed on the resistance switching layer.Type: ApplicationFiled: August 14, 2018Publication date: February 20, 2020Inventors: Chao-Hung WANG, Dai-Ying LEE, Kuang-Hao CHIANG, Yu-Hsuan LIN, Tsung-Ming CHEN
-
Publication number: 20200027488Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.Type: ApplicationFiled: October 9, 2018Publication date: January 23, 2020Inventors: Yu-Hsuan LIN, Chao-Hung WANG
-
Publication number: 20200026991Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.Type: ApplicationFiled: December 18, 2018Publication date: January 23, 2020Applicant: Macronix International Co., Ltd.Inventors: Yu-Hsuan Lin, Chao-Hung Wang, Ming-Hsiu Lee
-
Patent number: 10482953Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.Type: GrantFiled: August 14, 2018Date of Patent: November 19, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsuan Lin, Yu-Yu Lin, Feng-Min Lee, Chao-Hung Wang, Po-Hao Tseng, Kai-Chieh Hsu