Patents by Inventor Chao-Jui WANG
Chao-Jui WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10002802Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.Type: GrantFiled: May 26, 2017Date of Patent: June 19, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Tang Wang, Chia-Ming Chang, Shih-Che Lin, Chao-Jui Wang
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Patent number: 9991123Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.Type: GrantFiled: May 2, 2017Date of Patent: June 5, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFATURING CO., LTD.Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
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Publication number: 20170263509Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Sheng-Tang WANG, Chia-Ming CHANG, Shih-Che LIN, Chao-Jui WANG
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Publication number: 20170236716Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mei-Chun CHEN, Ching-Chen HAO, Wen-Hsin CHAN, Chao-Jui WANG
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Patent number: 9666495Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the cores in the first lot.Type: GrantFiled: December 13, 2013Date of Patent: May 30, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Tang Wang, Chia-Ming Chang, Shih-Che Lin, Chao-Jui Wang
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Patent number: 9647087Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.Type: GrantFiled: September 2, 2015Date of Patent: May 9, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
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Publication number: 20150380516Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mei-Chun CHEN, Ching-Chen HAO, Wen-Hsin CHAN, Chao-Jui WANG
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Patent number: 9136340Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.Type: GrantFiled: June 5, 2013Date of Patent: September 15, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
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Publication number: 20150168488Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the core in the first lot.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Tang WANG, Chia-Ming CHANG, Shih-Che LIN, Chao-Jui WANG
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Publication number: 20140361364Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.Type: ApplicationFiled: June 5, 2013Publication date: December 11, 2014Inventors: Mei-Chun CHEN, Ching-Chen HAO, Wen-Hsin CHAN, Chao-Jui WANG