Patents by Inventor Chao-Kai Chang

Chao-Kai Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11789259
    Abstract: A vision inspection and correction method, which uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in or out, shift, focus, diverge, and rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted. Then, the binocular images are aligned, and the inspector will implant the correction parameters during the image adjustment process into 3D projectors, VR (virtual reality), AR (augmented reality device), MR hybrid reality device and other equipment to adjust the binocular digital image parameters, so users have, or can provide to a lens maker, personalized adjustment for comfortable images of both eyes.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 17, 2023
    Assignee: PASSION LIGHT INC.
    Inventors: Jih-Yi Liao, Chung-Ping Chen, Tse-Yao Wang, Shan-Lin Chang, Ming-Cheng Tsai, Chia-Hung Lin, Ter-Chin Chen, Chao Kai Chang
  • Patent number: 11647280
    Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: May 9, 2023
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Fu-Cheng Chen, Chao-Kai Chang, Yao-Chang Hsieh
  • Publication number: 20230025324
    Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.
    Type: Application
    Filed: December 28, 2021
    Publication date: January 26, 2023
    Inventors: Fu-cheng Chen, Chao-kai Chang, Yao-chang Hsieh
  • Patent number: 11476772
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 18, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Publication number: 20220206291
    Abstract: A vision inspection and correction method, which mainly uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in/out/shift/focus/diverge/rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: Jih-Yi LIAO, Chung-Ping CHEN, Tse-Yao WANG, Shan-Lin CHANG, Ming-Cheng TSAI, Chia-Hung LIN, Ter-Chin CHEN, Chao Kai CHANG
  • Publication number: 20210126548
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Application
    Filed: July 31, 2020
    Publication date: April 29, 2021
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Patent number: 10791601
    Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 29, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Kai Chang, Chen-Yu Wang, Chang-Hseih Wu, Jai-Tai Kuo
  • Publication number: 20190289685
    Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Chao-Kai CHANG, Chen-Yu WANG, Chang-Hseih WU, Jai-Tai KUO
  • Patent number: 10412801
    Abstract: A light-emitting device includes a current source module having a first transistor, a first voltage control module providing a negative voltage and a second voltage control module having a second transistor. The second voltage control module is electrically connected to the current source module and the first voltage control module.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 10, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Kai Chang, Yi-Chao Lin, Chang-Hseih Wu, Jia-Tay Kuo
  • Patent number: 7562324
    Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: July 14, 2009
    Assignee: Chang Gung University
    Inventors: Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
  • Patent number: 7512525
    Abstract: A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: March 31, 2009
    Assignee: Chang Gung University
    Inventors: Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, Chao-Kai Chang
  • Patent number: 7437689
    Abstract: An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: October 14, 2008
    Assignee: Chang Gung University
    Inventors: Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Chao-Kai Chang
  • Publication number: 20080115098
    Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Applicant: CHANG GUNG UNIVERSITY
    Inventors: Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
  • Patent number: 7216322
    Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 8, 2007
    Assignee: Chang Gung University
    Inventors: Ming-Hong Lai, Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
  • Publication number: 20070033549
    Abstract: An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Applicant: Chang Gung University
    Inventors: Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Chao-Kai Chang
  • Publication number: 20060149525
    Abstract: The work proposes a model reduction method, the rational Arnoldi method with adaptive orders (RAMAO), to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 6, 2006
    Applicant: CHANG GUNG UNIVERSITY
    Inventors: Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, Chao-Kai Chang
  • Publication number: 20060053395
    Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 9, 2006
    Applicant: Chang Gung University
    Inventors: Ming-Hong Lai, Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
  • Publication number: 20050249423
    Abstract: A block decoding method and system capable of decoding and outputting data in a rotated direction, which has a Huffman decoding device, a zigzag device, an inverse quantizer, an inverse discrete cosine device, a data buffer and a controller. In this invention, a dynamically set decoding window is introduced to perform the complete JPEG decoding on blocks in the decoding window and the Huffman decoding on blocks out of the decoding window. When decoding and outputting one or more columns of blocks in the decoding window is complete, the decoding window is dynamically adjusted to a next location for decoding and obtaining a next column of block or a next plurality of columns of blocks.
    Type: Application
    Filed: April 15, 2005
    Publication date: November 10, 2005
    Applicant: Sunplus Technology CO., Ltd.
    Inventors: Yu-Chu Huang, Yi-Che Chen, Chao-Kai Chang