Patents by Inventor Chao-Kai Chang
Chao-Kai Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11789259Abstract: A vision inspection and correction method, which uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in or out, shift, focus, diverge, and rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted. Then, the binocular images are aligned, and the inspector will implant the correction parameters during the image adjustment process into 3D projectors, VR (virtual reality), AR (augmented reality device), MR hybrid reality device and other equipment to adjust the binocular digital image parameters, so users have, or can provide to a lens maker, personalized adjustment for comfortable images of both eyes.Type: GrantFiled: December 28, 2020Date of Patent: October 17, 2023Assignee: PASSION LIGHT INC.Inventors: Jih-Yi Liao, Chung-Ping Chen, Tse-Yao Wang, Shan-Lin Chang, Ming-Cheng Tsai, Chia-Hung Lin, Ter-Chin Chen, Chao Kai Chang
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Patent number: 11647280Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.Type: GrantFiled: December 28, 2021Date of Patent: May 9, 2023Assignee: SIGMASTAR TECHNOLOGY LTD.Inventors: Fu-Cheng Chen, Chao-Kai Chang, Yao-Chang Hsieh
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Publication number: 20230025324Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.Type: ApplicationFiled: December 28, 2021Publication date: January 26, 2023Inventors: Fu-cheng Chen, Chao-kai Chang, Yao-chang Hsieh
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Patent number: 11476772Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.Type: GrantFiled: July 31, 2020Date of Patent: October 18, 2022Assignee: EPISTAR CORPORATIONInventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
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Publication number: 20220206291Abstract: A vision inspection and correction method, which mainly uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in/out/shift/focus/diverge/rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Jih-Yi LIAO, Chung-Ping CHEN, Tse-Yao WANG, Shan-Lin CHANG, Ming-Cheng TSAI, Chia-Hung LIN, Ter-Chin CHEN, Chao Kai CHANG
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Publication number: 20210126548Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.Type: ApplicationFiled: July 31, 2020Publication date: April 29, 2021Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
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Patent number: 10791601Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.Type: GrantFiled: March 14, 2019Date of Patent: September 29, 2020Assignee: EPISTAR CORPORATIONInventors: Chao-Kai Chang, Chen-Yu Wang, Chang-Hseih Wu, Jai-Tai Kuo
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Publication number: 20190289685Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.Type: ApplicationFiled: March 14, 2019Publication date: September 19, 2019Inventors: Chao-Kai CHANG, Chen-Yu WANG, Chang-Hseih WU, Jai-Tai KUO
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Patent number: 10412801Abstract: A light-emitting device includes a current source module having a first transistor, a first voltage control module providing a negative voltage and a second voltage control module having a second transistor. The second voltage control module is electrically connected to the current source module and the first voltage control module.Type: GrantFiled: August 23, 2018Date of Patent: September 10, 2019Assignee: EPISTAR CORPORATIONInventors: Chao-Kai Chang, Yi-Chao Lin, Chang-Hseih Wu, Jia-Tay Kuo
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Patent number: 7562324Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.Type: GrantFiled: November 9, 2006Date of Patent: July 14, 2009Assignee: Chang Gung UniversityInventors: Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
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Patent number: 7512525Abstract: A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.Type: GrantFiled: January 5, 2005Date of Patent: March 31, 2009Assignee: Chang Gung UniversityInventors: Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, Chao-Kai Chang
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Patent number: 7437689Abstract: An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.Type: GrantFiled: August 8, 2005Date of Patent: October 14, 2008Assignee: Chang Gung UniversityInventors: Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Chao-Kai Chang
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Publication number: 20080115098Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.Type: ApplicationFiled: November 9, 2006Publication date: May 15, 2008Applicant: CHANG GUNG UNIVERSITYInventors: Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
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Patent number: 7216322Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.Type: GrantFiled: September 7, 2004Date of Patent: May 8, 2007Assignee: Chang Gung UniversityInventors: Ming-Hong Lai, Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
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Publication number: 20070033549Abstract: An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Applicant: Chang Gung UniversityInventors: Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Chao-Kai Chang
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Publication number: 20060149525Abstract: The work proposes a model reduction method, the rational Arnoldi method with adaptive orders (RAMAO), to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.Type: ApplicationFiled: January 5, 2005Publication date: July 6, 2006Applicant: CHANG GUNG UNIVERSITYInventors: Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, Chao-Kai Chang
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Publication number: 20060053395Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Applicant: Chang Gung UniversityInventors: Ming-Hong Lai, Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng
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Publication number: 20050249423Abstract: A block decoding method and system capable of decoding and outputting data in a rotated direction, which has a Huffman decoding device, a zigzag device, an inverse quantizer, an inverse discrete cosine device, a data buffer and a controller. In this invention, a dynamically set decoding window is introduced to perform the complete JPEG decoding on blocks in the decoding window and the Huffman decoding on blocks out of the decoding window. When decoding and outputting one or more columns of blocks in the decoding window is complete, the decoding window is dynamically adjusted to a next location for decoding and obtaining a next column of block or a next plurality of columns of blocks.Type: ApplicationFiled: April 15, 2005Publication date: November 10, 2005Applicant: Sunplus Technology CO., Ltd.Inventors: Yu-Chu Huang, Yi-Che Chen, Chao-Kai Chang