Abstract: A vision inspection and correction method, which uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in or out, shift, focus, diverge, and rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted. Then, the binocular images are aligned, and the inspector will implant the correction parameters during the image adjustment process into 3D projectors, VR (virtual reality), AR (augmented reality device), MR hybrid reality device and other equipment to adjust the binocular digital image parameters, so users have, or can provide to a lens maker, personalized adjustment for comfortable images of both eyes.

Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.

Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.

Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.

Abstract: A vision inspection and correction method, which mainly uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in/out/shift/focus/diverge/rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted.

Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.

Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.

Abstract: A light-emitting device has a stabilizing-current circuit, a current source having a high electron mobility transistor, and a light source electrically connected to the stabilizing-current circuit and the current source.

Abstract: A light-emitting device includes a current source module having a first transistor, a first voltage control module providing a negative voltage and a second voltage control module having a second transistor. The second voltage control module is electrically connected to the current source module and the first voltage control module.

Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

Abstract: A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Abstract: An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.

Abstract: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

Abstract: An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.

Abstract: The work proposes a model reduction method, the rational Arnoldi method with adaptive orders (RAMAO), to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

Abstract: A block decoding method and system capable of decoding and outputting data in a rotated direction, which has a Huffman decoding device, a zigzag device, an inverse quantizer, an inverse discrete cosine device, a data buffer and a controller. In this invention, a dynamically set decoding window is introduced to perform the complete JPEG decoding on blocks in the decoding window and the Huffman decoding on blocks out of the decoding window. When decoding and outputting one or more columns of blocks in the decoding window is complete, the decoding window is dynamically adjusted to a next location for decoding and obtaining a next column of block or a next plurality of columns of blocks.