Abstract: The present disclosure provides a Universal Flash Storage (UFS) memory module including an input/output interface, a flash memory, and a controller. The flash memory includes: a write buffer portion; and a normal storage portion having a plurality of logic units. The controller includes: a processor; a first register indicating a maximum size of the write buffer portion; a second register indicating an available size of the write buffer portion; and a third register. If the third register indicates the UFS memory module is in a shared buffer mode, the write buffer portion only includes a first shared buffer area. If the third register indicates the UFS memory module is in an advanced mode, the write buffer portion includes at least one dedicated buffer area, each corresponding to one of the plurality of logic units. The present disclosure also provides a controller, an electronic device and a method for operating a UFS memory module.

Abstract: A data storage device includes a data storage medium and a control unit. The control unit is electrically connected to the data storage medium. When switched to a command queue mode, the control unit is configured to receive a queue command comprising at least one task from a host, determine whether the at least one task is a ready-for-execution task, sort at least one ready-for-execution task and selectively reply the host with first queue status information. The first queue status information contains a task quantity corresponding to the at least one ready-for-execution task and at least one task serial number corresponding to the at least one sorted ready-for-execution task.

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method comprises: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

Abstract: A memory card controller coupled to a host device includes a processing circuit which is used for reading card specific data from a flash memory of a memory card to store the card specific data in a register wherein a multiply parameter and a basic capacity are marked in the card specific data and used for sending the card specific data to the host device to make the host device calculate a maximum capacity of the memory card according to the multiply parameter and the basic capacity marked in the card specific data.

Abstract: A storage device includes a data storage media and a control unit. The control unit is electrically coupled to the data storage media and configured for controlling the data storage media. The control unit is configured to receive a task assignment packet from a host. The task assignment packet includes a plurality of tasks and each of the tasks has a task ID. The control unit is configured to sort the tasks and generate an execution order for the tasks and reply the host with a task arrangement packet according to the execution order. A task execution method of the storage device and the host and a task execution method thereof are also provided.

Abstract: A method for accessing data in a circular block mode, executed by a processing unit, is introduced to contain the following steps. A read command and an LBA (Logical Block Address) are obtained from a host device through a first access interface. Logical block and page numbers are calculated according to the LBA, and a record associated with the logical block number is read from a storage mapping table, where the record contains a physical block number and a circular index. A physical page number is calculated according to the logical page number and the circular index. A read command is issued to a storage unit through a second access interface for reading data of the LBA from a region associated with the physical block number and the physical page number, and the data is replied to the host device through the first access interface.

Abstract: A data storage device includes a data storage medium and a control unit. The control unit is electrically connected to the data storage medium. When switched to a command queue mode, the control unit is configured to receive a queue command comprising at least one task from a host, determine whether the at least one task is a ready-for-execution task, sort at least one ready-for-execution task and selectively reply the host with first queue status information. The first queue status information contains a task quantity corresponding to the at least one ready-for-execution task and at least one task serial number corresponding to the at least one sorted ready-for-execution task.

Abstract: A storage device includes a data storage media and a control unit. The control unit is electrically coupled to the data storage media and configured for controlling the data storage media. The control unit is configured to receive a task assignment packet from a host. The task assignment packet includes a plurality of tasks and each of the tasks has a task ID. The control unit is configured to sort the tasks and generate an execution order for the tasks and reply the host with a task arrangement packet according to the execution order. A task execution method of the storage device and the host and a task execution method thereof are also provided.

Abstract: A method for accessing data in a circular block mode, executed by a processing unit, is introduced to contain the following steps. A read command and an LBA (Logical Block Address) are obtained from a host device through a first access interface. Logical block and page numbers are calculated according to the LBA, and a record associated with the logical block number is read from a storage mapping table, where the record contains a physical block number and a circular index. A physical page number is calculated according to the logical page number and the circular index. A read command is issued to a storage unit through a second access interface for reading data of the LBA from a region associated with the physical block number and the physical page number, and the data is replied to the host device through the first access interface.

Abstract: A 3D image-capturing method, a 3D camera and a level-alignment machine for a 3D camera are disclosed. The method includes the following steps: capturing a left- and a right-eye image by a left- and a right-eye camera, respectively; comparing the left- and right-eye images to observe similar columns between the left- and right-eye images; comparing the left- and right-eye images once again over the similar columns to observe similar rows between the left- and right-eye images; and, referring to the similar columns between the left- and right-eye images, vertically shifting the left- and right-eye images to horizontally align the left- and right-eye images to generate a 3D image.

Abstract: A 3D image-capturing method, a 3D camera and a level-alignment machine for a 3D camera are disclosed. The method includes the following steps: capturing a left- and a right-eye image by a left- and a right-eye camera, respectively; comparing the left- and right-eye images to observe similar columns between the left- and right-eye images; comparing the left- and right-eye images once again over the similar columns to observe similar rows between the left- and right-eye images; and, referring to the similar columns between the left- and right-eye images, vertically shifting the left- and right-eye images to horizontally align the left- and right-eye images to generate a 3D image.

Abstract: A method for generating a high quality up-scaled image includes: utilizing at least four pixels within a source image as reference pixels within the high quality up-scaled image, where the reference pixels are utilized as a portion of pixels within the high quality up-scaled image, and are utilized as reference for generating another portion of pixels within the high quality up-scaled image; and calculating at least one portion of three linear distribution values corresponding to three quarter points between two adjacent pixels of the reference pixels according to pixel values of the two adjacent pixels and adjusting the portion of the linear distribution values according to pixel values of at least three reference pixels of the four reference pixels, and generating at least one pixel within the high quality up-scaled image accordingly. An associated device is also provided.

Abstract: A method for performing de-noise processing includes: with regard to each direction of a plurality of directions, summing up absolute values of differences between a plurality of sets of first pixel values around a target pixel of an image to generate a first detection value, and with regard to each direction of at least a portion of the directions, selectively averaging at least one set of second pixel values around the target pixel to generate a second detection value; sorting a plurality of pixel values around the target pixel and generating a third detection value accordingly; and with regard to a specific direction of the directions, performing de-noise processing on the target pixel according to at least the former two of the first detection value, the third detection value, and the second detection value. An associated apparatus is also provided.

Abstract: A method for performing de-noise processing includes: with regard to each direction of a plurality of directions, summing up absolute values of differences between a plurality of sets of first pixel values around a target pixel of an image to generate a first detection value, and with regard to each direction of at least a portion of the directions, selectively averaging at least one set of second pixel values around the target pixel to generate a second detection value; sorting a plurality of pixel values around the target pixel and generating a third detection value accordingly; and with regard to a specific direction of the directions, performing de-noise processing on the target pixel according to at least the former two of the first detection value, the third detection value, and the second detection value. An associated apparatus is also provided.

Abstract: A method for generating a high quality up-scaled image includes: utilizing at least four pixels within a source image as reference pixels within the high quality up-scaled image, where the reference pixels are utilized as a portion of pixels within the high quality up-scaled image, and are utilized as reference for generating another portion of pixels within the high quality up-scaled image; and calculating at least one portion of three linear distribution values corresponding to three quarter points between two adjacent pixels of the reference pixels according to pixel values of the two adjacent pixels and adjusting the portion of the linear distribution values according to pixel values of at least three reference pixels of the four reference pixels, and generating at least one pixel within the high quality up-scaled image accordingly. An associated device is also provided.

Abstract: A method for performing color interpolation on a down-sampled Bayer image includes: with regard to at least one pixel to be interpolated in the down-sampled Bayer image, performing at least one pixel prediction operation according to pixel values of a plurality of neighboring pixels kept by a down-sampling operation, in order to generate at least one simulation pixel value of at least one corresponding simulation pixel of at least one neighboring pixel discarded by the down-sampling operation; and performing at least one color interpolation operation according to at least one pixel value of at least one neighboring pixel kept by the down-sampling operation and the at least one simulation pixel value, in order to generate a pixel value of the at least one pixel to be interpolated. An associated device is also provided.