Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer on the substrate; isolation structures extending through the dielectric layer into the substrate; and a floating gate on the dielectric layer and between the isolation structures, wherein the floating gate includes a first portion directly on the dielectric layer; and second portions on the sidewalls of the first portion.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.

Abstract: Disclosed are a plasma damage protection device and a plasma damage protection method. The plasma damage protection device is disposed in an integrated circuit. The plasma damage protection device includes a switch component and a transmission structure. The switch component is coupled between a reference power rail and a pad. The switch component is turned on or cut off according to a charge on the pad. The pad is coupled to a protected component. The transmission structure is configured to transmit the charge on the pad to a control end of the switch component during a back-end-of-line process. The switch component is turned on according to the charge on the pad during the back-end-of-line process.

Abstract: An electrostatic discharge protection circuit, including a discharge switch, a first transistor, an inverter, and a feedback circuit, is provided. The discharge switch is coupled between a first power rail and a second power rail, and may be turned on or cut off according to a control voltage. The first transistor has a first end coupled to the first power rail. A control end of the first transistor receives the control voltage. The inverter is coupled between a second end of the first transistor and a control end of the discharge switch. The feedback circuit is coupled between an output end and an input end of the inverter and is configured to determine whether to provide a turn-on path between the input end of the inverter and the second power rail according to the control voltage.

Abstract: An electrostatic discharge protection circuit, including a discharge switch, a first transistor, an inverter, and a feedback circuit, is provided. The discharge switch is coupled between a first power rail and a second power rail, and may be turned on or cut off according to a control voltage. The first transistor has a first end coupled to the first power rail. A control end of the first transistor receives the control voltage. The inverter is coupled between a second end of the first transistor and a control end of the discharge switch. The feedback circuit is coupled between an output end and an input end of the inverter and is configured to determine whether to provide a turn-on path between the input end of the inverter and the second power rail according to the control voltage.

Abstract: Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.

Abstract: An electrostatic discharge protection circuit including a silicon controlled rectifier and a transistor is provided. The silicon controlled rectifier includes a first end, a second end, and a third end. The first end of the silicon controlled rectifier is coupled to a first pad. The second end of the silicon controlled rectifier is coupled to a second pad. The transistor includes a first end, a second end, and a control end. The first end of the transistor is coupled to the first pad. The second end of the transistor is coupled to the second pad. The control end of the transistor is coupled to the third end of the silicon controlled rectifier.

Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.

Abstract: A manufacturing method for a multi-layer circuit board capable of being applied with electrical testing is provided. According to the multi-layer circuit board manufactured by the method, the multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.

Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

Abstract: A manufacturing method for a multi-layer circuit board is provided. According to the multi-layer circuit board manufactured by the manufacturing method, the multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.

Abstract: A carrier substrate and a method for manufacturing the carrier substrate are disclosed herein. The method includes the steps of: providing a core substrate; forming a build-up material layer on the core substrate; forming a via in the build-up material layer; forming a patterned photoresist layer on the build-up material layer covering a portion of the via and exposing an opening from uncovered portion of the via, and a wiring slot connected to the opening; and forming a metal-electroplated layer on the via and the wiring slot. In forming a trace according to the present invention, the metal-electroplated layer is formed as the trace and directly connected to the via, striding or not striding over the via. Additionally, in the carrier substrate structure, there is no need an annular ring to connect the trace to the via, and thus the wiring space is increased.

Abstract: A carrier substrate and a method for manufacturing the carrier substrate are disclosed herein. The method includes the steps of: providing a core substrate; forming a build-up material layer on the core substrate; forming a via in the build-up material layer; forming a patterned photoresist layer on the build-up material layer covering a portion of the via and exposing an opening from uncovered portion of the via, and a wiring slot connected to the opening; and forming a metal-electroplated layer on the via and the wiring slot. In forming a trace according to the present invention, the metal-electroplated layer is formed as the trace and directly connected to the via, striding or not striding over the via. Additionally, in the carrier substrate structure, there is no need an annular ring to connect the trace to the via, and thus the wiring space is increased.