Abstract: A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.

Abstract: Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer.

Abstract: Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer.